Programmable logic cell and array with bus repeaters

• US 5,218,240 A
• Filed: 08/25/1992
• Issued: 06/08/1993
• Est. Priority Date: 11/02/1990
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Concurrent Logic, Inc. (Microchip Technology Incorporated)
• Inventors: Browder, Edward H., Furtek, Frederick C., Camarota, Rafael C., Ho, Walford W.
• Primary Examiner(s): Hudspeth, David R.
• Application Number:
  US07/935,116
• Time in Patent Office: 287 Days
• Field of Search: 307/443, 307/243, 307/465, 307/469, 307/465.1, 307/303.2, 307/468, 307/481, 340/825.83, 340/825.87, 340/825.91
• US Class Current: 326/39
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17792 for operating speed

Abstract

A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell comprises eight inputs, eight outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network comprises a local, a turning and an express bus for each row and column of the array and repeater means for partitioning said buses of a given row or column so as to form bus segments. The bus network provides for transfer of data to the cells of the array without using the cells as individual wires.

Claims

1. In a two dimensional array of logic cells, each cell except those at the edges of the array having four nearest neighbors so as to form rows and columns of said cells, a bus network for transmitting signals within the array comprising:

a local bus, a turning bus and an express bus provided for every row and column of the array formed by said cells,

repeater means for driving said buses, said repeater means partitioning said buses of a given row or column so as to form bus segments, each bus segment spanning a plurality of said logic cells.

2. The apparatus of claim 1 wherein the repeater means forming the bus segments are aligned in rows and columns which partition said array of cells into rectangular blocks of said cells.

3. The apparatus of claim 1 wherein each local bus segment is connected to every cell spanned by that bus segment so as to provide an electrical connection between the cells and the bus network.

4. The apparatus of claim 1 wherein each turning bus segment provides an electrical connection to all orthogonal bus segments between a row of the array and a column of the array.

5. The apparatus of claim 1 wherein the express bus segment is connected solely to the two repeater means forming said express bus segment.

6. The apparatus of claim 1 wherein the repeater means is programmable to connect any bus connected to one side of the repeater means to any bus connected to one side of the repeater means to any bus connected to the other side of the repeater.

7. The apparatus of claim 1 wherein the repeater means provides electrical signal regeneration for each programmable connection.

8. The apparatus of claim 1 wherein the repeater means is programmable so as to select the electrical signal direction through the repeater means for a given bus connection.

9. A programmable logic array comprising:

a plurality of logic cells, wherein each cell except those at the edges of the array has four nearest neighbors, one to the left (or West), one to the right (or East), one above (or to the North) and one below (or to the South) so as to form an array in which said cells are aligned in rows and columns, and

clock distribution means for providing independent timing signals to said logic cells, said clock distribution means comprising one multiplexer for each column of the array, each multiplexer having a plurality of inputs and one output, said output being connected to each logic cell in the given column.

10. The apparatus of claim 9 wherein said multiplexer in the clock distribution means has four inputs, a first input to said multiplexer being a constant logical signal, said second input coming from an external timing source, said third input coming from an express bus and said fourth input coming from the output of a logic cell.

11. The apparatus of claim 9 wherein the timing signal provided to the logic cells of a given column of the array is independent from the timing signal of any other column of the array.