Multistep analog-to-digital converter with embedded correction data memory for trimming resistor ladders

• US 5,218,362 A
• Filed: 07/02/1992
• Issued: 06/08/1993
• Est. Priority Date: 07/02/1992
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Chin, Sing W., Mayes, Michael K.
• Primary Examiner(s): Logan, Sharon D.
• Application Number:
  US07/908,230
• Time in Patent Office: 341 Days
• Field of Search: 341/121, 341/120, 341/118, 341/156, 341/159, 341/155
• US Class Current: 341/121
• CPC Class Codes: H03M 1/069 by range overlap between successive stages or steps
• CPC Class Codes: H03M 1/1047 using an auxiliary digital/analogue converter for adding the correction values to the analogue signal H03M1/1052 takes precedence
• CPC Class Codes: H03M 1/145 the steps being performed sequentially in series-connected stages H03M1/141, H03M1/143, H03M1/16 take precedence

Abstract

An analog-to-digital converter (ADC) has at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages. A memory array embedded in the ADC stores a digital value corresponding to each tap point of the resistance ladder and thus to each reference voltage. During a first conversion cycle an estimated conversion value is generated based on comparison of the input voltage with the stepped series of reference voltages. The estimated conversion value corresponds to one of the resistor ladder tap points selected as being closest in voltage to the input voltage. In a second conversion cycle, a derived voltage based on the input voltage of the estimated conversion value, is compared with a smaller range of reference voltages to generate a finer resolution conversion value. In accordance with the present invention, the voltage on one of the two input nodes of the comparators used in the second conversion cycle is adjusted by an amount proportional to the digital value, stored in the ADC'"'"'s embedded memory, corresponding to the estimated conversion value from the first conversion cycle, thereby correcting for any non-uniformities in the resistances of the resistor ladder.

Claims

1. An analog-to-digital converter, comprising:

an input circuit that receives an input signal having an input voltage;

a resistor ladder circuit that generates a sequence of N stepped reference voltages, where N is an integer larger than four;

M comparator circuits that simultaneously compare said input voltage with M of said N stepped reference voltages and generate M binary comparison signals, wherein M≦

N and said M comparator circuits are coupled to said input circuit and said resistor ladder;

a digital encoder, coupled to said M comparator circuits, that encodes said M binary comparison signals to generate a multiple-bit first digital conversion value;

a programmable memory that stores a multiplicity of digital correction values, wherein said programmable memory is addressed by at least a subset of said first digital conversion value'"'"'s most significant bits and outputs a corresponding one of said multiplicity of digital correction values;

a digital-to-analog converter that converts said digital correction value output by said programmable memory into an analog correction voltage;

a circuit for generating a residual voltage corresponding to a selected one of said N stepped reference voltages, corresponding to said first digital conversion value, minus said input voltage, plus an offset voltage proportional to said analog correction voltage; and

means for converting said residual voltage into a second digital conversion value.

2. The analog-to-digital converter of claim 1,

said analog-to-digital converter comprising a single semiconductor integrated circuit;

said M comparator circuits including means for comparing said residual voltage with a second sequence of stepped reference voltages to generate a second set of M binary comparison signals; and

said residual voltage converting means including control circuitry coupled to said M comparator circuits and to said digital encoder, said control circuitry prompting said digital encoder to encode said second set of M binary comparison signals to generate said second digital conversion value.

3. An analog-to-digital converter, comprising:

an input circuit that samples an input voltage signal;

a resistor ladder having a multiplicity of resistors serially connected between first and second voltage supply nodes, said resistor ladder including N tap points at which N stepped reference voltages are generated, where N is an integer larger than four;

M comparator circuits, coupled to said input circuit and said resistor ladder, where M≦

N, each comparator circuit having two input nodes including a first input node on which a voltage signal corresponding to said input voltage signal is asserted;

said M comparator circuits comparing said asserted voltage signal with M of said N stepped reference voltages and generating a corresponding set of M binary comparison signals;

a digital encoder that encodes said M binary comparison signals to generate an X-bit initial digital conversion value, where X is at an integer greater than three;

a programmable memory that which stores a multiplicity of digital correction values, wherein said programmable memory is addressed by at least a subset of said X-bit initial digital conversion value'"'"'s most significant bits and outputs a corresponding one of said multiplicity of digital correction values;

a digital-to-analog converter that converts said digital correction value output by said programmable memory into an analog correction voltage;

a voltage adjustment circuit for adjusting a predefined voltage by an offset voltage proportional to said analog correction voltage, wherein said predefined voltage is selected from the set consisting of (A) said input voltage, (B) one of said N stepped reference voltages selected in accordance with said initial digital conversion value, and (C) a combination of said input voltage and said selected one of said N stepped reference voltages; and

means for generating a second digital conversion value in accordance with said adjusted predefined voltage.

4. The analog-to-digital converter of claim 3,

wherein said voltage adjustment circuit generates a residual voltage corresponding to a selected one of said N stepped reference voltages, corresponding to said initial digital conversion value, minus said input voltage, plus an offset voltage proportional to said analog correction voltage;

and

said generating means including means for converting said residual voltage into a second digital conversion value.

5. The analog-to-digital converter of claim 3,

wherein said voltage adjustment circuit includes coupled switched capacitors for generating a voltage comprising a predefined combination of said input voltage, said selected one of said N stepped reference voltages, and said analog correction voltage.

6. A method of metering an analog input signal'"'"'s voltage so as to generate a digital output signal, said the steps of the method comprising:

storing in a digital memory circuit a multiplicity of digital correction values, each digital correction value corresponding to at least one reference voltage in a predefined set of reference voltages;

receiving an input signal having an input voltage;

comparing said input voltage with at least a first subset of said predefined set of reference voltages to produce a first set of comparison signals;

encoding said first set of comparison signals to generate a first digital conversion value having multiple bits;

retrieving from said digital memory circuit one of said digital correction values in accordance with said first digital conversion value having multiple bits;

converting said retrieved digital correction value into an analog correction voltage;

comparing said input voltage with at least a second subset of said predefined set of reference voltages, adjusted by an offset voltage proportional to said analog correction voltage, to produce a second set of comparison signals; and

encoding said second set of comparison signals to generate a second digital conversion value.

7. The method of claim 6, said second comparing step including:

generating a residual voltage corresponding to a selected one of said predefined set of reference voltages, corresponding to said first digital conversion value, minus said input voltage, plus an offset voltage proportional to said analog correction voltage; and

comparing said residual voltage with at least said second subset of said predefined set of reference voltages to produce said second set of comparison signals.