Electro-optical device
First Claim
Patent Images
1. An electro-optical device comprising:
- a pair of substrates;
an electro-optical modulating layer provided between said substrates;
a column control line provided on one of said substrates;
two row control lines R1 and R2 provided on said one of said substrates;
an electrode provided on said one of said substrates between said two row control lines;
a first p-channel transistor P1 and a first n-channel transistor N1 which are provided on said one of said substrates and connected to said column control line at gate terminals of the transistors P1 and N1, and to said electrode at one of source and drain terminals of said first p-channel transistor P1 and at one of source and drain terminals of said first n-channel transistor N1 ;
a second p-channel transistor P2 provided on said one of said substrates and connected to the row control line R1 at one of source and drain terminals of the transistor P2, to the row control line R2 at a gate terminal of the transistor P2, and to the other one of the source and drain terminals of said first n-channel transistor N1 at the other one of the source and drain terminals of said second p-channel transistor P2 ; and
a second n-channel transistor N2 provided on said one of said substrates and connected to the row control line R2 at one of source and drain terminals of the transistor N2, to the row control line R1 at a gate terminal of the transistor N2, and to the other one of the source and drain terminals of said first p-channel transistor P1 at the other one of the source and drain terminals of said second n-channel transistor N2.
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Accused Products
Abstract
An electro-optical device having plural picture elements arranged in a matrix form, including thin film transistor assemblies each including a complementary thin film transistor which is connected to each picture element and comprises P-channel thin film transistor and N-channel thin film transistor, and P-channel and N-channel thin film transistors for driving the complementary thin film transistor. One signal line used for driving one thin film transistor of the thin film transistor assembly for a picture element is commonly used for driving one thin film transistor of another thin film transistor assembly for another picture element adjacent to the picture element.
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Citations
20 Claims
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1. An electro-optical device comprising:
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a pair of substrates; an electro-optical modulating layer provided between said substrates; a column control line provided on one of said substrates; two row control lines R1 and R2 provided on said one of said substrates; an electrode provided on said one of said substrates between said two row control lines; a first p-channel transistor P1 and a first n-channel transistor N1 which are provided on said one of said substrates and connected to said column control line at gate terminals of the transistors P1 and N1, and to said electrode at one of source and drain terminals of said first p-channel transistor P1 and at one of source and drain terminals of said first n-channel transistor N1 ; a second p-channel transistor P2 provided on said one of said substrates and connected to the row control line R1 at one of source and drain terminals of the transistor P2, to the row control line R2 at a gate terminal of the transistor P2, and to the other one of the source and drain terminals of said first n-channel transistor N1 at the other one of the source and drain terminals of said second p-channel transistor P2 ; and a second n-channel transistor N2 provided on said one of said substrates and connected to the row control line R2 at one of source and drain terminals of the transistor N2, to the row control line R1 at a gate terminal of the transistor N2, and to the other one of the source and drain terminals of said first p-channel transistor P1 at the other one of the source and drain terminals of said second n-channel transistor N2. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An electro-optical device comprising:
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a pair of substrates; an electro-optical modulating layer provided between said substrates; pixels Amn (1≦
m≦
s;
1≦
n≦
t; and
s, t, m, and n are natural numbers) arranged in a matrix of s×
t on one of said substrates, the pixels Am1, Am2, . . . , Amt being arranged on an mth row, and the pixels A1n, A2n, . . . , Asn being arranged on an nth column;row control lines R1, R2, . . . , Rs+1 provided on said one of said substrates, the row control line Rm being provided on the mth row, and the row control line Rs+1 being provided on an (s+1)th row; and column control lines C1, C2, . . . , Ct provided on said one of said substrates, the column control line Cn being provided on the nth column, the pixel AXY (1≦
X≦
s-1, 1≦
Y≦
t) comprising;an electrode EXY provided on said one of said substrates; a p-channel transistor PXY1 and an n-channel transistor NXY1 which are provided on said one of said substrates and connected to the column control line CY at gate terminals of the transistors PXY1 and NXY1, and to said electrode EXY at one of source and drain terminals of the transistor PXY1 and at one of source and drain terminals of the transistor NXY1 ; a p-channel transistor PXY2 provided on said one of said substrates and connected to the row control line RX at one of source and drain terminals of the transistor PXY2, to the row control line RX+1 at a gate terminal of the transistor PXY2, and to the other one of the source and drain terminals of the transistor NXY1 at the other one of the source and drain terminals of the transistor PXY2 ; and an n-channel transistor NXY2 provided on said one of said substrates and connected to the row control line RX+1 at one of source and drain terminals of the transistor NXY2, to the row control line RX at a gate terminal of the transistor NXY2, and to the other one of the source and drain terminals of the transistor PXY1 at the other one of the source and drain terminals of the transistor NXY2, and the pixel A.sub.(X+1)Y comprising; an electrode E.sub.(X+1)Y provided on said one of said substrates; a p-channel transistor P.sub.(X+1)Y1 and an n-channel transistor N.sub.(X+1)Y1 which are provided on said one of said substrates and connected to the column control line CY at gate terminals of the transistors P.sub.(X+1)Y1 and N.sub.(X+1)Y1, and to said electrode E.sub.(X+1)Y at one of source and drain terminals of the transistor P.sub.(X+1)Y1 and at one of source and drain terminals of the transistor N.sub.(X+1)Y1 ; a p-channel transistor P.sub.(X+1)Y2 provided on said one of said substrates and connected to the row control line RX+1 at one of source and drain terminals of the transistor P.sub.(X+1)Y2, to the row control line RX+2 at a gate terminal of the transistor P.sub.(X+1)Y2, and to the other one of the source and drain terminals of the transistor N.sub.(X+1)Y1 at the other one of the source and drain terminals of the transistor P.sub.(X+1)Y2 ; and an n-channel transistor N.sub.(X+1)Y2 provided on said one of said substrates and connected to the row control line RX+2 at one of source and drain terminals of the transistor N.sub.(X+1)Y2, to the row control line RX+1 at a gate terminal of the transistor N.sub.(X+1)Y2, and to the other one of the source and drain terminals of the transistor P.sub.(X+1)Y1 at the other one of the source and drain terminals of the transistor N.sub.(X+1)Y2.
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9. An electro-optical device comprising:
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a pair of substrates; an electro-optical modulating layer provided between said substrates; a column control line provided on one of said substrates; two row control lines R1 and R2 provided on said one of said substrates; an electrode provided on said one of said substrates between said two row control lines; two first p-channel transistors P1 and P11 and two first n-channel transistors N1 and N11 which are provided on said one of said substrates and connected to said column control line at gate terminals of the transistors P1, P11, N1, and N11, and to said electrode at one of source and drain terminals of each of said two first p-channel transistors P1 and P11 and at one of source and drain terminals of each of said two first n-channel transistors N1 and N11 ; two second p-channel transistors P2 and P22 which are provided on said one of said substrates and connected to the row control line R1 at one of source and drain terminals of each of said two second p-channel transistors P2 and P22, to the row control line R2 at gate terminals of the transistors P2 and P22, and to the other one of the source and drain terminals of each of said two first n-channel transistors N1 and N11 at the other one of the source and drain terminals of corresponding one of said two second p-channel transistors P2 and P22 ; and two second n-channel transistors N2 and N22 which are provided on said one of said substrates and connected to the row control line R2 at one of source and drain terminals of each of said two second n-channel transistors N2 and N22, to the row control line R1 at gate terminals of the transistors N2 and N22, and to the other one of the source and drain terminals of each of said two first p-channel transistors P1 and P11 at the other one of the source and drain terminals of corresponding one of said two second n-channel transistors N2 and N22. - View Dependent Claims (10, 11, 12, 13, 14)
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15. An electro-optical device comprising:
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a pair of substrates; an electro-optical modulating layer provided between said substrates; a column control line provided on one of said substrates; two row control lines R1 and R2 provided on said one of said substrates; two electrodes provided on said one of said substrates between said two row control lines R1 and R2 ; a first p-channel transistor P1 and a first n-channel transistor N1 provided on said one of said substrates and connected to said column control line at gate terminals of the transistors P1 and N1, and to one of said two electrodes at one of source and drain terminals of said first p-channel transistor P1 and at one of source and drain terminals of said first n-channel transistor N1 ; a second p-channel transistor P2 provided on said one of said substrates and connected to the row control line R1 at one of source and drain terminals of the transistor P2, to the row control line R2 at a gate terminal of the transistor P2, and to the other one of the source and drain terminals of said first n-channel transistor N1 at the other one of the source and drain terminals of said second p-channel transistor P2 ; a second n-channel transistor N2 provided on said one of said substrates and connected to the row control line R2 at one of source and drain terminals of the transistor N2, to the row control line R1 at a gate terminal of the transistor N2, and to the other one of the source and drain terminals of said first p-channel transistor P1 at the other one of the source and drain terminals of said second n-channel transistor N2 ; a third p-channel transistor P3 and a third n-channel transistor N3 which are provided on said one of said substrates and connected to said column control line at gate terminals of the transistors P3 and N3, and to the other one of said two electrodes at one of source and drain terminals of said third p-channel transistor P3 and at one of source and drain terminals of said third n-channel transistor N3 ; a fourth p-channel transistor P4 provided on said one of said substrates and connected to the row control line R1 at one of source and drain terminals of the transistor P4, to the row control line R2 at a gate terminal of the transistor P4, and to the other one of the source and drain terminals of said third n-channel transistor N3 at the other one of the source and drain terminals of said fourth p-channel transistor P4 ; and a fourth n-channel transistor N4 provided on said one of said substrates and connected to the row control line R2 at one of source and drain terminals of the transistor N4, to the row control line R1 at a gate terminal of the transistor N4, and to the other one of the source and drain terminals of said third p-channel transistor P3 at the other one of the source and drain terminals of said fourth n-channel transistor N4. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsHiroki, Masaaki, Yamazaki, Shunpei
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Primary Examiner(s)Sikes, William L.
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Assistant Examiner(s)MAI, HUY KIM
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Application NumberUS07/836,797Time in Patent Office476 DaysField of Search359/59, 359/54, 340/784, 340/719, 257/104, 257/190, 257/288, 257/297US Class Current349/48CPC Class CodesG02F 1/136245 having complementary transi...G02F 1/1368 in which the switching elem...G09G 2300/0809 Several active elements per...G09G 2300/0823 used to establish symmetry ...G09G 2330/08 Fault-tolerant or redundant...G09G 3/3648 using an active matrix G09G...G09G 3/3659 the addressing of the pixel...H01L 27/12 the substrate being other t...
