Method and a circuit for encoding a digital signal to determine the scalar product of two vectors, and corresponding DCT processing
First Claim
1. A circuit for encoding a digital signal to determine the scalar product value of two vectors of the same dimension p, one of said vectors, {ak}1p including dedicated components of determined value and the other vector {xk}1p including variable components, said dedicated and variable components being encoded on N bits, said scalar product value being expressed in the form of encoded partial sums fi of binary variables xki, xki designating the binary value of the bit of order i of said variable components xk and each of said encoded partial product sums fi being expressed at the bit level as an encoded elementary partial sum fij for each bit of order j, wherein i and j are integers in the range 0 to N-1, each encoded elementary partial sum expressed as the product xki.akj taking one of the binary values akij, where akj designates the binary values of the bit of order j of said dedicated component ak, said circuit comprising:
- a logical encoding circuit for receiving as inputs said binary values of the bit of order i of said variable components, and for generating a logical combination of said binary values of order i; and
a plurality of N multiplexers, each of said multiplexers of order j including one input for receiving said logical combination of said binary values of order i of said variable component and a further input for receiving said binary values of order j of said dedicated component, together with a zero value, and each of said multiplexers delivering a corresponding partial sum fij, said partial sum fi being obtained by concatenating each of said elementary partial sums fij.
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Abstract
The invention relates to encoding a digital signal to determine the scalar product of two vectors. For two vectors of the same dimension p, one having dedicated components {ak} and the other having variable components {xk}, the scalar product value ##EQU1## is reduced to partial sums fi of binary variables xki, which binary variables take one of the values of the fixed components ak depending on the values of the xki having m possible values. Dedicated logic encoding makes it possible to take the variables xki and generate a plurality of bit level elementary partial sums fij for each bit of rank j in fi, having 2m possible values, by varying the binary values akj of the bits of rank j. A two-dimensional interconnection matrix causes each rank j bit akj to correspond to a single value of the elementary partial sums fij, and together these bits define the corresponding partial sum fi. The invention is applicable to circuits for image processing or for data compression by the discrete cosine transform.
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Citations
11 Claims
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1. A circuit for encoding a digital signal to determine the scalar product value of two vectors of the same dimension p, one of said vectors, {ak}1p including dedicated components of determined value and the other vector {xk}1p including variable components, said dedicated and variable components being encoded on N bits, said scalar product value being expressed in the form of encoded partial sums fi of binary variables xki, xki designating the binary value of the bit of order i of said variable components xk and each of said encoded partial product sums fi being expressed at the bit level as an encoded elementary partial sum fij for each bit of order j, wherein i and j are integers in the range 0 to N-1, each encoded elementary partial sum expressed as the product xki.akj taking one of the binary values akij, where akj designates the binary values of the bit of order j of said dedicated component ak, said circuit comprising:
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a logical encoding circuit for receiving as inputs said binary values of the bit of order i of said variable components, and for generating a logical combination of said binary values of order i; and a plurality of N multiplexers, each of said multiplexers of order j including one input for receiving said logical combination of said binary values of order i of said variable component and a further input for receiving said binary values of order j of said dedicated component, together with a zero value, and each of said multiplexers delivering a corresponding partial sum fij, said partial sum fi being obtained by concatenating each of said elementary partial sums fij. - View Dependent Claims (2, 3)
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3. A circuit as claimed in claim 1, wherein for vectors of dimension p=1, said one vector includes one dedicated component a1 =a and said other vector includes one variable component x1 =x, said variable component being encoded using a two complements code and said partial sum fi being expressed as fi =(-2xi +xi+1 +xi+2).a, where i, i+1, i+2 designate bit orders of successive binary variables of said variable component x, said logical encoding circuit comprising a modified Booth encoder for receiving said successive binary variables of said variable component, and for generating and delivering to said multiplexers:
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a shift check parameter Si expressed as a logical combination of the form
space="preserve" listing-type="equation">S.sub.i =x.sub.i+1 ⊕
x.sub.i+2,a non-zero check parameter Ni expressed as a logical combination of the form
space="preserve" listing-type="equation">N.sub.i =x.sub.i.x.sub.i+1.x.sub.i+2 +x.sub.i.x.sub.i+1.x.sub.i+2, anda complement control parameter Ci expressed as a logical combination of the form Ci =xi, each multiplexer of order j receiving said binary variable aj of order j of said dedicated component so as to deliver a corresponding elementary partial sum fij.
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4. A circuit for encoding a digital signal to determine the scalar product value of two vectors of the same dimension p, one of said vectors, {ak}1p including dedicated components of determined value and the other vector {xk}1p including variable components, said dedicated and variable components being encoded on N bits, said scalar product value being expressed in the form of encoded partial sums fi of binary variables xki, xki designating the binary value of the bit of order i of said variable components xk and each of said encoded partial product sums fi being expressed at the bit level as an encoded elementary partial sum fij for each bit of order j, wherein i and j are integers in the range 0 to N-1, each encoded elementary partial sum expressed as the product xki.akj taking one of the binary values akij, where akj designates the binary values of the bit of order j of said dedicated component ak, said circuit comprising:
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dedicated logic encoding means for generating a plurality of said encoded elementary partial sums fij on the basis of said binary values xki of said variable components xk, by evaluating 2m possibilities wherein m=2p -1 if p≧
2 or m=2 if p=1, by varying the binary values akj of the bits of the same order j of the said dedicated component ak, andat least one two-dimensional interconnection matrix of dimension 2m N, said at least one matrix having an input for receiving said encoded elementary partial sums fij and an input for receiving said binary values akj of the bits of the same order j of said dedicated components, and the at least one matrix comprising electrical connections causing each of said binary values of rank j of said dedicated components to correspond to one value and to one value only of said bit level encoded elementary partial sums fij, said sum fi being obtained by concatenating each of said elementary partial sums. - View Dependent Claims (5, 6, 7)
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6. A circuit as claimed in claim 4 wherein for vectors of dimension p=1, one of said vectors including a dedicated component a1 =a and said other of said vectors including a variable component x1 =x, said variable component being encoded using a two complements code and said partial sum fi being expressed as fi =(-2xi +xi +1+xi +2).a where i, i+1, i+2 designate integer bit orders of binary values of said variable component x, said dedicated encoding circuit comprises:
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an input circuit having an input for receiving said binary values xi, xi+1, xi+2 of corresponding order of said variable component x, said input circuit including three inverters for generating complemented values xi, xi+1, xi+2 of said binary values and an output for delivering said binary values and said complemented binary values, and a plurality of logic gates for receiving said binary values and said complemented binary values and for delivering the corresponding values of said elementary partial sums fij.
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7. A circuit as claimed in claim 4 in which said two dimensional matrix comprises a programmable mesh network connected between conductors connected to the input of said matrix and conductors connected to its output, an electrical connection being formed between an input and an output so as to enable each output to correspond to an input of corresponding value.
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8. Apparatus for calculating the scalar product of two vectors of dimension 2q, with q>
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dedicated logic encoding means for generating a plurality of said encoded elementary partial sums fij on the basis of said binary values xki of said variable components xk, by evaluating 2m possibilities wherein m=2p -1 if p≧
2 or m=2 if p=1, by varying the binary values akj of the bits of the same order j of the said dedicated component ak, andat least one two-dimentional interconnection matrix of dimension 2m N, said at least one matrix having an input for receiving said encoded elementary partial sums fij and an input for receiving said binary values akj of the bits of the same order j of said dedicated components, and the at least one matrix comprising electrical connections causing each of said binary values of rank j of said dedicated components to correspond to one value and to one value only of said bit level encoded elementary partial sums fij, and said sum fi being obtained by concatenating each of said elementary partial sums, one of said circuits using each pair of subvectors relating to dedicated components and to variable components to generate a corresponding partial sum ei, fi, gi, hi, and said apparatus further comprising summing means for receiving and summing together each partial sum ei, fi, gi, hi. - View Dependent Claims (9, 10, 11)
- 1, wherein each vector is subdivided into q subvectors of dimension 2, said apparatus comprising a plurality of circuits each comprising a circuit for encoding a digital signal to determine the scalar product value of two vectors of the same dimension p, one of said vectors, {ak}1p including dedicated components of determined value and the other vector {xk}1p including variable components, said dedicated and variable components being encoded on N bits, said scalar product value being expressed in the form of encoded partial sums fi of binary variables xki, xki designating the binary value of the bit of order i of said variable components xk and each of said encoded partial product sums fi being expressed at the bit level as an encoded elementary partial sum fij for each bit of order j, wherein i and j are integers in the range 0 to N-1, each encoded elementary partial sum expressed as the product xki.akj taking one of the binary values akij, where akj designates the binary values of the bit of order j of said dedicated component ak, said circuit comprising;
Specification