EPROM source bias circuit with compensation for processing characteristics
First Claim
1. Circuitry for improving the programming efficiency of a floating gate transistor when it is programmed by hot electron programming techniques during a programming cycle, the transistor having respective gate, drain and source nodes, the circuitry comprising:
- a reference voltage generator for generating a reference voltage during said programming cycle, said reference voltage being process-dependent on the conductivity of said floating gate transistor, wherein said reference voltage varies in dependence on the programming characteristics of said floating gate transistor; and
voltage biasing means responsive to said reference voltage for biasing the voltage on said source node during programming at a low source voltage when said transistor conductivity is low and at a higher source voltage when said transistor conductivity is high,wherein the drain-to-source voltage of the transistor being programmed is high when said transistor conductivity is low, and low when said transistor conductivity is high.
0 Assignments
0 Petitions
Accused Products
Abstract
An electrically programmable read only memory (EPROM) source bias circuit provides a bias voltage at the source of an EPROM transistor which may vary with EPROM processing characteristics. The source bias circuit includes a reference voltage generator which generates a reference voltage which varies with EPROM transistor cell conductivity, and a source bias element which sets the voltage on the source node of the EPROM transistor during programming. The circuit functions to provide a greater amount of source bias to a higher-conductivity EPROM cell during programming, and to apply a lower source bias voltage to low conductivity EPROM cells. Programming efficiency of the EPROM transistor is improved, and yield of EPROM devices employing the circuit is enhanced.
-
Citations
24 Claims
-
1. Circuitry for improving the programming efficiency of a floating gate transistor when it is programmed by hot electron programming techniques during a programming cycle, the transistor having respective gate, drain and source nodes, the circuitry comprising:
-
a reference voltage generator for generating a reference voltage during said programming cycle, said reference voltage being process-dependent on the conductivity of said floating gate transistor, wherein said reference voltage varies in dependence on the programming characteristics of said floating gate transistor; and voltage biasing means responsive to said reference voltage for biasing the voltage on said source node during programming at a low source voltage when said transistor conductivity is low and at a higher source voltage when said transistor conductivity is high, wherein the drain-to-source voltage of the transistor being programmed is high when said transistor conductivity is low, and low when said transistor conductivity is high. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. An electrically programmable read only memory (EPROM) integrated circuit device comprising a plurality of EPROM cells, each cell including a floating gate transistor having respective gate, drain and source nodes, which may be selectively programmed during a programming cycle, wherein said cells are arranged in a plurality of columns, each column in turn comprising a plurality of EPROM cells, only one of which cells in a particular column being selected for programming during a given programming cycle, remaining cells in a particular column being characterized as non-selected cells, said EPROM integrated circuit device including circuitry for improving programming efficiency of the floating gate transistors of the EPROM memory cells when they are selectively programmed by hot electron programming techniques, comprising:
-
a reference signal generator for generating a process-dependent reference signal during the programming cycle, said reference signal dependent on the conductivity of a mirror floating gate transistor included in said reference signal generator and whose conductivity tracks that of a selected floating gate transistor being programmed; and voltage biasing means responsive to said reference signal for biasing the voltage on the source node of said selected floating gate transistor being programmed, including means for biasing said source node of said selected floating gate transistor being programmed at a low source voltage when said transistor conductivity of said selected floating gate transistor being programmed is low and for biasing said source node of said selected floating gate transistor being programmed at a higher source voltage when the conductivity of said selected floating gate transistor being programmed is high; wherein the drain-to-source voltage of the selected floating gate transistor being programmed is high when said transistor conductivity of said selected floating gate transistor being programmed is low, and said drain-to-source voltage is low when said transistor conductivity of said selected floating gate transistor being programmed is high. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
-
Specification