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EPROM source bias circuit with compensation for processing characteristics

  • US 5,218,571 A
  • Filed: 01/09/1992
  • Issued: 06/08/1993
  • Est. Priority Date: 05/07/1990
  • Status: Expired due to Term
First Claim
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1. Circuitry for improving the programming efficiency of a floating gate transistor when it is programmed by hot electron programming techniques during a programming cycle, the transistor having respective gate, drain and source nodes, the circuitry comprising:

  • a reference voltage generator for generating a reference voltage during said programming cycle, said reference voltage being process-dependent on the conductivity of said floating gate transistor, wherein said reference voltage varies in dependence on the programming characteristics of said floating gate transistor; and

    voltage biasing means responsive to said reference voltage for biasing the voltage on said source node during programming at a low source voltage when said transistor conductivity is low and at a higher source voltage when said transistor conductivity is high,wherein the drain-to-source voltage of the transistor being programmed is high when said transistor conductivity is low, and low when said transistor conductivity is high.

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