Interprocessor switching network

• US 5,218,602 A
• Filed: 04/04/1991
• Issued: 06/08/1993
• Est. Priority Date: 04/04/1991
• Status: Expired due to Term

• Current Assignee: Alcatel-Lucent USA, Inc. (Nokia Corporation)
• Original Assignee: DSC Communications Corp. (Nokia Corporation)
• Inventors: Grant, Elwyn E., McCoy, James K., Hanson, Gary D., Nimon, Kimmy F.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Jung, Min
• Application Number:
  US07/680,327
• Time in Patent Office: 796 Days
• Field of Search: 370/58.1, 370/60, 370/94.1, 370/58.2, 370/61, 370/85.1, 370/85.13, 370/94.3
• US Class Current: 370/390
• CPC Class Codes: H04L 2012/563 Signalling, e.g. protocols, reference model
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/255 Control mechanisms for ATM switching fabrics
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/555 Error detection

Abstract

A digital switching network for providing simultaneous connections among user processors of processor-based communications equipment. The user processors act as originators and destinations of data communications packets. Packet data connections are through node controllers, which communicate with gateways, which are connected to a switching network via packet links. Control messages are communicated between node controllers, gateways, and an interchange control subsystem via various control message links. All control message processing and packet data transmissions are synchronized with a packet frame synchronization signal, and processing tasks performed by each of the network subsystems are pipelined so that they occur simultaneously. Service requests are queued in a central queue in the interchange control system. The synchronization and queueing simplify the control messages that are required to set up and release the connections.

Claims

1. A switching network for providing data communication between user processors of processor-based communications equipment, where the user processors are arranged in clusters, each cluster having a node controller, comprising:

a switching matrix for establishing point-to-point connections between originating processors and destination processors;

an interchange control system in communication with said switching matrix, said interchange control system having at least one request buffer for receiving service requests from said originating processors, and having a connection controller for maintaining a central queue of said service requests and for establishing connections within said switching matrix in accordance with said service requests;

a plurality of gateways for providing access from the node controllers to said switching matrix for transmissions of the data and for providing access from said node controllers to said interchange control system for transmissions of said control messages;

at least one gateway group controller for controlling the operation of said gateways;

wherein said interchange control system and said gateway group controller are programmed to recognize certain control messages, including said service requests;

a timing generator for providing a synchronization signal to said interchange control system and said gateway group controller, such that all processing of said control messages occurs in periodic cycles.

2. The switching network of claim 1, wherein said switching matrix includes memory for storing connection commands during one cycle for execution during a subsequent cycle.

3. The switching network of claim 1, wherein said switching matrix comprises matrix elements having packet link drivers for each of a number of outbound packet links, wherein each of said link drivers is independently enabled by a connection command.

4. The switching network of claim 1, wherein said switching matrix has an outbound port for broadcasting packets to all of said gateways simultaneously.

5. The switching network of claim 1, wherein said request buffer includes a multiplexer for multiplexing said service requests from an associated one of said gateways to said connection controller.

6. The switching network of claim 1, wherein said request buffer includes memory for storing path acknowledgements from said connection controller during one cycle and interface circuitry for transferring them to an associated gateway during a subsequent cycle.

7. The switching network of claim 1, wherein said request buffer generates and broadcasts release acknowledgements to all its associated gateways simultaneously.

8. The switching network of claim 1, wherein said request buffer sends path acknowledgements and release acknowledgements during the same cycle.

9. The switching network of claim 1, wherein said request buffer includes an originator request memory for determining which of said gateways have issued a service request during a particular cycle.

10. The switching network of claim 1, wherein said connection controller includes a new request queue for storing current service requests and a holdover queue for storing deferred service requests and a controller for reading said queues.

11. The switching network of claim 10, wherein said connection controller further comprises a request selector for examining incoming service requests on a priority basis and placing a new request in said new request queue.

12. The switching network of claim 1, wherein said connection controller is programmed to simultaneously queue service requests, examine pending queues, establish connections, and transfer connections to said switching matrix during a single cycle.

13. The switching network of claim 1, wherein said connection controller maintains a node status memory for monitoring the busy status of nodes associated with said gateways.

14. The switching network of claim 1, wherein said connection controller has a connect buffer for storing connection commands, and a controller for performing memory swaps on alternate banks of said buffer.

16. The switching network of claim 1, wherein said switching matrix has means for broadcasting a packet, such that said packet is simultaneously delivered to all nodes associated with said gateways.

17. The switching network of claim 1, wherein said protocol consists only of requests for service, request acknowledgements, path acknowledgments, and release acknowledgements.

28. The switching network of claim 1, further comprising means for varying the period of said packet frame synchronization signal.

15. The switching network of claim i, wherein said connection controller has a state controller programmed to process a service request and its associated packet data transfer during a predetermined number of cycles.

18. A switching network for providing data communication between user processors of a processor-based communication equipment, where the user processors are arranged in clusters, each cluster representing a communications node, comprising:

a switching matrix for establishing point-to-point connections between originating processors and destination processors;

an interchange control system in communication with said switching matrix, said interchange control system having a request buffer for receiving service requests from said originating processors and having a connection controller for generating connection commands in response to said service requests and sending said connection commands to said switching matrix;

a plurality of gateways for sending and receiving packet data between said originating processors and said destination processors, wherein said gateways provide access by said processors to said switching matrix for transmission of said data and provide access by said processors to said interchange control circuit for transmission of said service requests;

at least one gateway group controller for controlling the operation of said gateways;

wherein said interchange control system and said gateway group controllers are programmed such that their operations are synchronized to a packet frame synchronization signal that defines a current frame period for each current data packet to be communicated; and

a timing generator for providing a timing signal to said interchange control system and said gateway group controller that defines said packet frame synchronization signal.

19. The switching network of claim 18, wherein said switching matrix is programmed to respond to said connection commands for a current data packet during said current frame period.

20. The switching network of claim 18, wherein said gateways are programmed such that a current data packet is transferred between said gateways during said current frame period.

21. The switching network of claim 18, wherein said connection controller is programmed to make path connections for a next packet frame transfer during said current packet frame.

22. The switching network of claim 18, wherein said connection controller is further programmed to transfer said path connections to said switching matrix during said current frame.

23. The switching network of claim 18, and further comprising node controllers for controlling the activities of the cluster of processors, wherein said node controllers are also synchronized to said packet frame synchronization signal.

24. The switching network of claim 23, wherein said node controllers are programmed to check for path acknowledgements during said current frame period.

25. The switching network of claim 18, wherein said buffer circuit further generates release acknowledgements, and wherein said interchange control circuit is programmed to transfer a release acknowledgement associated with the transfer of a current packet frame during said current frame period.

26. The switching network of claim 25, wherein said interchange control circuit is programmed to transfer said release acknowledgements to each of said gateways during said current frame period.

27. The switching network of claim 25, wherein said switching network includes a packet broadcast means for transferring said release acknowledgements to each of said gateways.

29. A switching network for providing data communication between user processors of processor-based communications equipment, where the user processors are arranged in clusters, each having a node controller, comprising:

a switching matrix for establishing a point-to-point connections between originating processors and destination processors;

an interchange control system in communication with said switching matrix, said interchange control system having a request buffer for queueing service requests from said originating processors, and having a connection controller for maintaining said queue and for establishing connections within said switching matrix in accordance with said service requests;

a plurality of gateways for sending and receiving packet data between said originating processors and said destination processors and for sending and receiving control messages to and from said interchange control system, said control messages including said service requests, wherein said gateway circuits provide access from the node controllers to said switching matrix for transmissions of the data and provide access from said node controllers to said interchange control circuit for transmissions of said control messages;

packet links connecting said switching matrix to said gateways, for transferring packet data;

a gateway bus connecting said originating processors and said destination processors to said gateways;

a first level of service request links connecting said gateways to said interchange control circuit;

a second level of service request links connecting said request buffer to said connection controller within said interchange control circuit;

a connect bus connecting said connection controller to said switching matrix; and

timing lines for providing a synchronization signal to said switching network, said interchange control circuit, and said gateway circuit, such that all processing occurs in periodic cycles.

30. The switching network of claim 29, and further comprising a controller for generating said synchronization signal and a bus for transmitting said signal from said maintenance controller to said switching matrix and to said interchange control circuit.

31. The switching network of claim 29, wherein timing signals are further transmitted to said gateway circuit from said interchange control circuit, for timing control messages.

32. The switching network of claim 29, wherein said switching matrix includes a packet broadcast means for transmitting timing signals to said node controllers for synchronizing the operation of said node controllers.

33. A method for providing connections between an originating processor and a destination processor for the purpose of communicating digital data, in accordance with a set of connection command protocols that need not include requests to release a connection, comprising the steps of:

receiving packet data from an originating processor at an origination gateway, wherein said packet data includes an address of a server gateway and a destination processor;

sending a service request from said origination gateway to an interchange control circuit;

forming a point-to-point connection between said origination gateway and said server gateway if neither gateway is busy;

transferring said data from said originating processor to said destination processor;

wherein said receiving, sending, forming, and transferring steps are synchronized such that connection releases occur automatically as a result of lapsed interval of time.

34. The method of claim 33, and further comprising the step of maintaining a central queue of said service requests.

35. The method of claim 33, wherein said step of forming a point-to-point connection is performed with respect to a current service request during the same packet period as said step of transferring said data with respect to a previous second service request.

36. The method o claim 33, and further comprising the step of acknowledging said step of forming a point-to-point connection, wherein said acknowledging step is performed during the same packet frame period with respect to a current frame as said step of forming a point-to-point connection for that frame.

37. A method for providing connections between an originating processor and a destination processor for the purpose of communicating digital data, in a network having an interchange control circuit for generating connection commands and gateways for providing an interface to origination and destination nodes, comprising the steps of:

providing a timing signal representing a packet frame period;

sending a path acknowledgement from an interchange control circuit to a gateway associated with a originating processor node within said packet frame period for a current data packet;

transferring said current data packet within said packet frame period to a destination processor node, using a switching matrix in communication with said gateway;

sending a release acknowledgement from said interchange control circuit to said gateway within said packet frame period for said current data packet;

wherein each of said steps occurs during the same packet frame period.

38. The method of claim 37, and further comprising the step of generating a path acknowledgement for a next subsequent packet within said interchange control circuit during the same packet frame period.

39. The method of claim 37, and further comprising the step of generating connection commands from said interchange control circuit to said switching matrix for a next subsequent packet during the same packet frame period.

40. The method of claim 37, and further comprising the step of transferring connection commands to said switching matrix during the same packet frame period.