Data link controller with autonomous in tandem pipeline circuit elements relative to network channels for transferring multitasking data in cyclically recurrent time slots

• US 5,218,680 A
• Filed: 03/15/1990
• Issued: 06/08/1993
• Est. Priority Date: 03/15/1990
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kuhl, Daniel C., Lee, Timothy V., Farrell, Joseph K., Gordon, Jeffrey S.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Lim, Krisna
• Application Number:
  US07/495,232
• Time in Patent Office: 1,181 Days
• Field of Search: 370/84, 370/60.1, 370/95.1, 370/77, 370/53, 370/68, 395/800, 395/325, 395/200
• US Class Current: 709/215
• CPC Class Codes: H04L 69/28 Timers or timing mechanisms used in protocols
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A "single-chip" integrated circuit device, useful in ISDN digital voice and data telephone applications, links plural channels of a data communication network with memory and CPU components of a data processing system. The device couples to the system via a bus that may be shared by other devices, and bidirectionally exchanges service information signals with the system CPU, and communication data signals with system memory. The service information includes device control information furnished by the CPU, and (channel and device) status information prepared by the device. The device contains multiple logic circuit units, operating in relative functional autonomy, and buffer memory units for storing service information and data. Units which interface to the network operate in synchronism with network communication processes. Units which interface to the system bus operate in asynchronous relation to network processes. Synchronous units which handle data are configured to form plural stage pipelines, in each direction of communication, which eases timing requirements at the bus interface. Status information is stored queued in memory unit storage spaces dedicated to the channels; each queue configured so that the system CPU can retrieve status information representing plural events in one channel in one coherent bus operation. The device is partitioned further to provide discretely separate internal paths for transferring service and data signals relative to the system. Service signal transfers to and from system CPU and directed by the CPU. Data signal transfers to and from system memory are directed by a DMA control unit in the device.

Claims

1. A data link control (DLC) device for connection between a data communication network and a bus connecting to CPU (central processing unit) and memory subsystems of a data processing system, said bus being subject to having multiple connections linking said data processing system to multiple devices, including said DLC device, data being transferred between said DLC device and multiple channels in said data communication network in cyclically recurrent time division time slots assigned to individual ones of said data communication network channels, data being transferred between said DLC device and said memory subsystem, via said bus, in asynchronous relation to associated data communication processes in said data communication network channels and respective said recurrent time slots, aid DLC device comprising:

memory means having storage spaces dedicated to said data communication network channels, the space dedicated to each of said channels including subspaces reserved for storing data being transferred between the respective channel of said data communication network and said DLC device and subspaces reserved for storing control information defining data processing operations to be performed by said DLC device on said data that is being transferred;

plural autonomous special purpose logic circuit elements connected in tandem between said data communication network and said memory means to form at least one plural-stage data processing pipeline relative to said channels, each said pipeline conveying data between said data communication network and said memory means and performing plural processing operations to selectively modify said data as it is conveyed, logic circuit elements forming discrete processing stages in each said pipeline operating during each of said cyclically recurrent time slots dedicated to an active one of said channels to perform data processing tasks on data being conveyed relative to the respective channel through the respective pipeline stage, logic elements forming different stages in any one said pipeline performing different data processing tasks on data being conveyed through the respective channel;

whereby each said pipeline serves as a multitasking data processing array relative to data undergoing transfer relative to each said active channel and as both a multiprocessing and multitasking array relative to data undergoing transfer relative to all active said channels; and

means coupled to said memory means and said bus for transferring data relative to individual said channels, between storage spaces in said memory means assigned to respective channels and storage spaces in said memory subsystem assigned to the same channels.

2. A DLC device in accordance with claim 1 wherein said data communication network channels include at least one channel which when active operates in a full duplex mode relative to a remote station connected to said data communication network, in order to convey "receive" data originating at said remote station to said DLC device while concurrently transmitting "transmit" data from said DLC device to said remote station, and wherein said DLC device pipelines comprise:

a multi-stage transmit pipeline, for conveying said transmit data from said memory means to said data communication network while processing said transmit data, and a multi-stage receive pipeline for conveying said receive data from said data communication network to said memory means while processing said receive data.

3. A DLC device in accordance with claim 2 wherein said network channels convey data simultaneously in different communication formats with different communication protocols and wherein:

said memory means contains storage spaces dedicated to each said channel for storing channel configuration register control information defining the type of communication function which the channel is currently performing; and

wherein said DLC device includes;

a channel configuration register common to all channels for storing the channel configuration register control information of each channel while the DLC device is performing operations to advance movement of data through the respective channel;

supervisory autonomous logic elements coupled to said channel configuration register and individual stages in said transmit and receive pipelines, said supervisory autonomous elements operating in synchronism with said pipeline stages, and conditioning said stages to perform processing tasks on data in transmit through said stages, said operations defined in part by the contents of said configuration control register;

whereby data can be transferred between said memory means and said memory subsystem in a format common to all channels and exchanged between said DLC device and said data communication network in diverse formats commensurate with respective channel configurations.

4. A DLC device in accordance with claim 3 wherein said channel configuration register control information is useful to configure a plurality of said channels for concurrently communicating digitized voice and data arranged in an HDLC (high level data link control) protocol between said data communication network and said memory subsystem, and wherein said autonomous elements constituting said pipeline stages perform the tasks required to accommodate said voice and HDLC data communications concurrently.

5. A DLC device in accordance with claim 4 wherein:

said autonomous logic elements constituting stages of said transmit pipeline process transmit data in transmit through said transmit pipeline, and contain logic effective relative to channels configured for transmitting data in said HDLC protocol for embedding HDLC frame delimiting symbols and Cyclic Redundancy Check (CRC) symbols into the transmit data of respective HDLC channels, on the fly, as said data is conveyed through said transmit pipeline from said device memory means to said data communication network; and

said logic elements constituting stages of said receive pipeline process receive data in transmit through said receive pipeline, and contain logic effective relative to channels configured for receiving data in accordance with HDLC protocols to perform processing tasks to strip HDLC frame delimiting symbols from receive data arranged in said HDLC protocol and to perform CRC checks on said receive data, on the fly, as said receive data is conveyed through said pipeline from said data communication network to said memory means.

6. A DLC device in accordance with claim 5 wherein:

said memory means and said autonomous logic elements constituting said transmit and receive pipelines operate at a rate sufficient to sustain concurrent service relative to at least 32 full duplex channels in said data communication network, with aggregate data rates in each channel of 128 kbps.

7. A DLC device in accordance with claim 5 wherein:

the entire DLC device is contained on a single LSI chip.

8. A DLC device in accordance with claim 5 wherein:

said data communication network contains one or more active channels operating in a full duplex mode;

said autonomous logic elements which constitute stages of said pipelines that interface directly to said data communication network interface to said full duplex channels on said data communication network in cyclically repetitive time slots dedicated to respective said full duplex channels, and operate during each such time slot to receive from 0 to n bits from the respective full duplex channel and to transmit from 0 to n bits to the respective full duplex channel, where n is greater than 2; and

said autonomous logic elements constituting stages in said transmit and receive pipelines process data being conveyed respectively to and from each said full duplex channel in bit-parallel formats.

9. A DLC device in accordance with claim 8 wherein said data received and transmitted at said data communication network interface relative to each said full duplex channel, during a said time slot assigned to the respective channel, is transferred only in short duration bursts occupying a small portion of the respective time slot, whereby a major portion of each respective time slot is available for use by said DLC device for establishing various operating states associated with said data communication network channels in the autonomous elements constituting said pipelines.

10. A DLC device in accordance with claim 9 wherein:

said memory means contains storage spaces reserved to each said channel for storing state control information for each said pipeline stage relative to the respective channel, said state control information defining instantaneous task processing states of each said pipeline stage relative to the respective channel.

11. A DLC device in accordance with claim 10 comprising:

means coupled to said memory means and each element constituting a stage in said pipeline for controlling bidirectional transfers of state control information between said memory means and each said pipeline stage during each of said time slots;

the state information transferred from the memory means to each pipeline stage during any time slot setting the respective stage into a task processing state corresponding to the state it was in at the end of the last previous recurrence of the same time slot, and the state information transferred from each pipeline stage to the memory means during each time slot representing the final task processing state of the respective stage in the respective slot;

whereby said pipeline stages are conditioned during successive recurrences of a time slot assigned to a channel to continuously perform processing tasks relative to that channel.

12. A DLC device according to claim 11 wherein:

said DLC device is contained on a single LSI semiconductor chip.

13. A DLC device in accordance with claim 1 wherein:

said memory means contains storage space reserved to each channel for storing event status information defining processing events occurring in the respective channel; and

wherein said device comprises;

means operating in synchronism with at least one of said pipelines for collecting process event status information relative to channel process events occurring in said pipeline;

means for storing said collected event status information in said memory means spaces dedicated therefor; and

means for rendering said stored status information accessible to said CPU subsystem of said processing system, through a circuit path extending through said DLC device and said bus which presents minimal interference with transfers of communication data between said memory means and said memory subsystem of said data processing system.

14. A DLC device in accordance with claim 13 wherein:

said memory means spaces reserved to each channel for storing channel process event status information are configured to simultaneously store plural sets of information representing plural process events occurring in respective channels at different times, and said means for storing said collected process event status information stores channel process event status information representing plural channel process events occurring at different times in one channel in separate memory means storage spaces reserved to that one channel for that purpose.

15. A DLC device according to claim 14 including:

an autonomous interrupt management (INT) logic element interfacing to said pipeline stages of said DLC device and to said memory means of said DLC device, said INT logic element operating to collect said process event status information, to manage transfer of said process event status information to said DLC device memory means, and to instigate transfers of interrupt request signals from said DLC device to said CPU subsystem for prompting said CPU subsystem to retrieve said stored process event status information from said DLC device memory means.

16. A DLC device according to claim 15 wherein all of said autonomous logic elements and said memory units of said DLC device are contained on a single LSI semiconductor chip.

17. A DLC device in accordance with claim 1 comprising:

an autonomous DMA control (DMAC) logic element, interfacing to said memory subsystem via said bus, for directly controlling addressing of said memory subsystem, and for transferring communication data between said memory means of said DLC device and said memory subsystem.

18. A DLC device according to claim 17 wherein:

said memory means includes storage spaces reserved to said DMAC element for storing control information defining operations to be conducted by said DMAC element relative to individual said channels;

said control information including information defining addresses in said memory subsystem to and from which communication data is to be transferred relative to respective channels.

19. A DLC device according to claim 18 including:

a slave I/O (SIO) logic element, interfacing to said CPU subsystem of said data processing system via said bus, said SIO element coupling said CPU subsystem with said DLC device memory means for enabling said CPU subsystem to transfer information to said memory means and retrieve information from said memory means with minimal interference to operations concurrently being directed by said DMAC element for transferring communication data relative to said memory subsystem.

20. A DLC device according to claim 19 wherein:

said information that can be transferred by said CPU subsystem to said DLC device memory means via said SIO element includes said control information for defining operations to be conducted by said DMAC element relative to individual said channels.

21. A DLC device according to claim 20 wherein:

said DLC device is contained on a single LSI semiconductor chip.

22. A DLC device according to claim 19 wherein:

said DLC device memory means stores channel status information relative to process events occurring in individual said channels; and

said information that can be retrieved from said DLC device memory means by said CPU subsystem via said SIO element includes said process event status information.

23. A DLC device according to claim 22 wherein:

said DLC device is contained on a single LSI semiconductor chip.

24. A DLC device according to claim 18 wherein:

said control information stored in said DLC device memory means includes sets of device control block information stored relative to individual said channels, each control block set effectively defining a series of data transfer operations to be conducted by said DLC device for transferring a block of multiple bytes of data between said memory subsystem and said DLC device memory means relative to the respective channel, and wherein said stored control block sets contain one or more chaining indications; and

said DMAC logic element is responsive to each said stored chaining indication, upon completing data transfer operations defined by the control block set containing the respective chaining indication, to retrieve another control block set from said memory subsystem which defines additional data transfer operations to extend the completed data transfer operations, whereby an operation in process relative to any channel is extended automatically by said DLC device without intervention of said CPU subsystem.

25. A DLC device according to claim 18 wherein:

said memory subsystem contains storage spaces configured by said CPU subsystem as circular buffers;

individual said circular buffer spaces being reserved by said CPU subsystem to individual said channels of said DLC device for storage of data being transferred between said DLC device memory means and said memory subsystem relative to respective said channels; and

said DMAC logic elementy of said DLC device is responsive to said control information stored in said DLC device memory means for managing transfers of data from data storage spaces reserved to said channels in said DLC device memory means to said circular buffer spaces reserved to respective channels, and for managing containment of said data within predetermined boundaries of said circular buffer spaces.

26. A DLC device according to claim 1 wherein said DLC device pipelines are adapted to perform discrete processing tasks relative to individual said channels during cyclically recurrent time division time slots reserved to respective said channels, and wherein said DLC device memory means comprises a plurality of discrete random access memory (RAM) storage units including:

a first RAM unit associated with said channels for storing data en route between said bus and said DLC device pipelines;

a second RAM unit for storing state control information relative to each of said channels defining task processing states of logic elements in said DLC device which constitute discrete stages in said DLC device pipelines relative to processes being conducted in said pipelines relative to respective channels; and

a third RAM unit for storing control information for controlling operations of said DLC device for transferring data between said first RAM unit and said memory subsystem of said data processing system.

27. A DLC device according to claim 26 wherein:

said DLC device is contained on a single LSI semiconductor chip.

28. A data link control (DLC) device for connection between a data communication network and a bus connecting to CPU (central processing unit) and memory subsystems of a data processing system, said bus being subject to having multiple connections linking said system to multiple devices, including said DLC device, data being transferred between said DLC device and multiple channels in said data communication network in cyclically recurrent time division time slot assigned to individual ones of said channels, data being transferred between said device and said memory subsystem, via said bus, in asynchronous time relation to associated data communication process in said data communication network channels and respective said recurrent time slots, said DLC device comprising:

memory means having storage spaces dedicated to said data communication network channels, the space dedicated to each said network channel including subspaces reserved for storing data being transferred between the respective network channel and said DLC device and subspaces reserved for storing control information defining data processing operations to be performed by said device on said data that is being transferred;

plural autonomous special purpose logic circuit elements connected in tandem between said data communication network and said memory means to form at least one plural-stage data processing pipeline relative to said network channels, each said pipeline conveying data between said data communication network and said memory means and performing plural data processing operations on said data to selectively modify said data as it is conveyed, logic circuit elements forming discrete processing stages in each said pipeline operating during each of said cyclically recurrent time slots dedicated to an active one of said network channels to perform data processing tasks on data being conveyed relative to that network channel through the respective pipeline stage, logic elements forming different stages in any one of said pipelines performing different data processing tasks on said data as it is passed through the respective pipeline;

whereby each said pipeline serves as a multitasking data processing array relative to said data undergoing transfer relative to each said active network channel and as both a multiprocessing and multitasking array relative to data undergoing transfer relative to all active said network channels;

means coupled to said memory means and said bus for transferring data relative to individual said network channels between storage spaces in said memory means assigned to respective said network channels and storage spaces in said memory subsystem assigned to the same network channels;

wherein said network channels carry data simultaneously in plural different data communication formats, and include at least one channel operating in a full duplex mode, relative to a remote station attached to said data communication network, to convey data from the remote station to said DLC device (receive data) while concurrently transmitting data supplied by said DLC device (transmit data) to said remote station, and said pipelines comprise;

a multi-stage transmit pipeline, for conveying transmit data from said memory means to said data communication network while processing said data, and a multi-stage receive pipeline for conveying receive data from said data communication network to said memory means;

wherein said memory means contains storage spaces dedicated to each channel for storing channel configuration register control information defining the data communication format of the respective channel, and said DLC device contains a channel configuration register common to all channels for storing the channel configuration register control information of each channel while the device is performing operations to advance movement of data through the respective channel;

wherein said device further comprises supervisory autonomous logic elements coupled to said channel configuration register and individual stages in said transmit and receive pipelines, aid supervisory elements operating in synchronism with said pipeline stages, and conditioning said pipeline stages to perform processing tasks on data in transit through said stages, said operations defined in part by the contents of said configuration control register;

whereby data can be transferred between said memory means and said memory subsystem in a format common to all channels and exchanged between said device and said data communication network in diverse formats commensurate with respective channel configurations;

wherein said channel configuration register control information is useful to configure a plurality of said channels for concurrently communicating digitized voice and data arranged in HDLC (high level data link control) protocol between said data communication network and said memory subsystem, and wherein said autonomous elements constituting said pipeline stages perform the data processing tasks required to accommodate said voice and HDLC data concurrently;

wherein autonomous logic elements constituting stages of said transmit pipeline process transmit data in transit through said transmit pipeline, and operate relative to channels in said data communication network that are configured for transmitting data in HDLC protocol to embed HDLC frame delimiting symbols and Cyclic Redundancy Check (CRC) check symbols into the transmit data of respective HDLC channels, on the fly, as said data is conveyed through said transmit pipeline from said device memory means to said data communication network;

wherein autonomous logic elements constituting stages of said receive pipeline process receive data in transit through said receive pipeline, and are effective relative to channels in said data communication network that are carrying receive data arranged in said HDLC protocol format to perform processing tasks to strip HDLC frame delimiting symbols from respective HDLC data and to perform CRC checks on said data, on the fly, as said respective data is conveyed through said pipeline from said data communication network to said memory means;

wherein said autonomous logic elements which constitute stages of said pipelines that interface directly to said data communication network interface to said full duplex channels on said data communication network in cyclically repetitive time slots dedicated to respective said full duplex channels, and operate during each such time slot to receive from 0 to n bits from the respective channel on the data communication network and to transmit from 0 to n bits to the respective channel on the data communication network, where n is greater than 2;

wherein said autonomous logic elements constituting stages in said transmit and receive pipelines are adapted to handle data being conveyed respectively to and from each said duplex channel in bit-parallel formats;

wherein said data received and transmitted at said data communication network interface, relative to each said full duplex channel is transferred only in short duration bursts occupying a small portion of the time slot allocated to the respective channel, whereby a major portion of each such allocated time slot is available to be used by said DLC device for changing operating stages of said pipeline elements relative to different said channels;

wherein said memory means contains storage spaces reserved to each said channel for storing state control information for each said pipeline stage relative to the respective channel;

said state control information defining instantaneous task processing states of each said pipeline stage relative to the respective channel;

said DLC device further comprising supervisory means coupled to said memory means and said pipeline elements for controlling bidirectional transfer of said state control information between said memory means and each of said pipeline stages during each said time slot;

the state control information transferred from said memory means to said pipeline stages at the beginning of each time slot serving to set respective stages to processing states they were in at the end of the last prior recurrence of the same time slot;

the state control information transferred from said pipeline stages to said memory means at the end of each time slot representing final processing states of respective stages for the respective slot;

said supervisory means comprising;

a special purpose resource managing (RSM) element for managing the cyclic saving and restoration of states between said elements in said pipeline sections and said memory means in synchronism with said time slots;

said RSM element providing starting and ending indications to said pipeline elements for directing said pipeline elements to start and end processing tasks relative to a channel associated with a current slot;

said pipeline elements asserting DONE indications to said RSM element in response to said ending indications when the current slot is one assigned to an active channel;

said pipeline elements further providing continuous output indications of their processing states during each slot;

said RSM element directing saving of said processing states of said pipeline elements to said memory means in response to said DONE indications from respective pipeline elements; and

said DONE indications being delayable by said pipeline elements to allow for said pipeline elements to reach stable processing states from which processing can be resumed without ambiguity.

29. A DLC device in accordance with claim 28 wherein said RSM element includes:

means coupled to the data communication network interface for receiving signals indicating beginnings of successive said time slots;

means responsive to said beginning of slot signals for providing successive ending and starting indications to said pipeline elements;

means interactive with said memory means prior to receipt of each beginning of slot signal for retrieving configuration control (CCR) information indicating if the currently occurring time slot is assigned to an active channel;

means interactive with said memory means upon receipt of the beginning of slot signal for retrieving configuration control (pre-CCR) information indicating if the slot then beginning is or is not assigned to an active channel;

means responsive to said DONE indications from said pipeline elements when said CCR information indicates that an active channel slot is ending for directing the saving of processing state indications relative to said slot from said pipeline elements to said memory means; and

means responsive to said pre-CCR information indicating that the slot then beginning is assigned to an active channel for directing loading of state control information, relative to the respective channel, from said memory means to said pipeline elements.

30. A DLC device according to claim 29 wherein:

said DLC device is contained on a single LSI semiconductor chip.

31. A data link control (DLC) device for connection between a bit-serial data communication network and a bit-parallel data transfer bus, said data communication network containing multiple bit-serial data communication channels, said bus connecting said DLC device with memory and CPU (central processing unit) subsystems of a data processing system, said bus being connectable to other devices besides said DLC device and being subject to contention between said DLC device and said other devices, said DLC device exchanging communication data bit-serially with individual channels of said data communication network, in cyclically recurrent time division time slots assigned to respective channels, said DLC device comprising:

first and second RAM storage units, each having storage spaces reserved to individual ones of said data communication network channels;

said reserved storage spaces in said first RAM unit forming storage queues structured for storing plural bytes of receive data, plural bytes of transmit data, and plural bytes of control information, relative to each said channel, said receive data in each said queue comprising data received bit-serially from a respective channel in said data communication network during periods of recurrence of said time slots assigned to the respective channel, said transmit data in each queue comprising data which is to be transferred bit-serially to a respective channel in said data communication network in periods of recurrence of said time slots assigned to the respective channel, and said control information in each queue defining positions of individual data byte storage spaces to which a next byte of receive data is to be transferred from a respective channel in said data communication network and from which a next byte of transmit data is to be transferred to the respective network channel;

said reserved spaces in said second RAM unit including spaces for holding control state information defining instantaneous processing states of said device relative to time slots assigned to respective said channels;

a first plurality of autonomous special purpose logic circuit elements connected in tandem between said network and said first RAM unit to form a plural-stage receive pipeline in which said receive data received from individual said channels is handled and processed by said DLC device during time slots assigned to the respective channels;

said elements constituting said receive pipeline operating in synchronism with said assigned time slots for transporting said receive data of respective channels from said network to respective receive data storage queues in said first RAM unit;

elements constituting individual stages in said receive pipeline selectively performing various processing tasks on said receive data as it is transferred through respective said stages;

including tasks for converting said receive data from serial to parallel form and tasks for selectively processing and removing protocol information contained in said receive data;

whereby said receive pipeline operates as a multitasking processing array, relative to receive data handled during time slots assigned to a single network channel, and as both a multiprocessing and a multitasking array relative to receive data handled in time slots assigned to all channels;

a second plurality of autonomous special purpose logic circuit elements connected in tandem between said network and said first RAM unit to form a plural-stage transmit pipeline relative to transmit data being transferred from said first RAM unit to said data communication network channels during said time slots assigned to respective channels, said elements constituting said transmit pipeline operating in synchronism with said assigned time slots for transporting said transmit data from respective transmit data storage queues in said first RAM unit to said data communication network channels in said time slots assigned to respective channels. Said elements constituting individual stages of said transmit pipeline performing various processing tasks on said transmit data as it passes through respective stages, including tasks for converting said transmit data from parallel to serial format and tasks for selectively inserting protocol delimiting characters into said data;

whereby said transmit pipeline acts as a multitasking array relative to transmit data handled in time slots assigned to a single one of said channels, and as both a multiprocessing and a multitasking array relative to transmit data handled in the time slots assigned to all channels; and

means coupled to said first and second RAM units and said bus for transferring said receive data and said transmit data relative to said channels between respective data storage queues in said first RAM unit and said memory subsystem.

32. A data link control (DLC) device for connection between a bit-serial data communication network and a bit-parallel data transfer bus, said network containing multiple bit-serial data communication channels, said bit-parallel data transfer bus connecting said DLC device with memory and CPU (central processing unit) subsystems of a data processing system, said bit-parallel data transfer bus being connectable to other devices besides said DLC device and being subject to contention between said DLC device and said other devices, said DLC device operating to exchange communication data bit-serially with individual channels of said network, in cyclically recurrent time division time slots assigned to respective channels, said DLC device comprising:

first and second RAM storage units, each having storage spaces reserved to individual ones of said network channels;

said reserved storage spaces in said first RAM unit forming storage queues structured for storing plural bytes of receive data, plural bytes of transmit data, and plural bytes of control information, relative to each said channel, said receive data in each queue comprising data received bit-serially from a respective network channel in periods of recurrence of said time slots assigned to the respective channel, said transmit data in each queue comprising data to be transferred bit-serially to a respective network channel in periods of recurrence of said time slots assigned to the respective channel, and said control information in each queue defining positions of individual data byte storage spaces to which a next byte of receive data is to be transferred from a respective network channel and from which a next byte of transmit data is to be transferred to the respective network channel;

said reserved spaces in said second RAM unit including spaces for holding control state information defining instantaneous processing states of said device relative to time slots assigned to respective channels;

a first plurality of autonomous special purpose logic circuit elements connected in tandem between said network and said first RAM unit to form a plural-stage receive pipeline in which said receive data of individual said channels is handled and processed by said DLC device during time slots assigned to the respective channels;

said elements constituting said receive pipeline operating in synchronism with said assigned time slots for transporting said receive data of respective channels from said network to respective receive data storage queues in said first RAM unit;

elements constituting individual stages in said receive pipeline selectively performing various processing tasks on said receive data as it is transferred through respective stages;

including tasks for converting said receive data from serial to parallel form and tasks for selectively processing and removing protocol information contained in said receive data;

whereby said receive pipeline operates as a multitasking processing array, relative to receive data handled during time slots assigned to a single network channel, and as both a multiprocessing and multitasking array relative to receive data handled in time slots assigned to all network channels;

a second plurality of autonomous special purpose logic circuit elements connected in tandem between said network and said first RAM unit to form a plural-stage transmit pipeline relative to transmit data being transferred from said first RAM unit to said network channels during said time slots assigned to respective channels, said elements constituting said transmit pipeline operating in synchronism with said assigned time slots for transporting said transmit data from respective transmit data storage queues in said first RAM unit to said network channels in said time slots assigned to respective channels;

said elements constituting individual stages of said transmit pipeline performing various processing tasks on said transmit data as it passes through respective stages, including tasks for converting said transmit data from parallel to serial format and tasks for selectively inserting protocol delimiting characters into said transmit data;

whereby said transmit pipeline stages act as a multitasking array relative to transmit data handled in time slots assigned to one of said channels, and as both a multiprocessing and multitasking array relative to transmit data handled in the time slots assigned to all of said channels; and

means coupled to said first and second RAM units and said bit-parallel data transfer bus for transferring said receive and transmit data relative to said channels between respective data storage queues in said first RAM unit and said memory subsystem; and

wherein

said network slots are assignable concurrently to multiple channels carrying voice and HDLC formatted data;

during any said time slot a variable number of x data bits is transferable at said data communication network interface relative to a channel respectively assigned to said any slot;

where x can range from 0 to n and n is at least 8;

said elements in said receive and transmit pipelines include layer 1 interfacing elements (RL1, TL1), which interface to said network during each slot for receiving and transferring data bit serially relative to a respective channel, validation elements (RV, TV) coupled to said layer 1 interfacing elements for exchanging data with said layer 1 interfacing elements in bit parallel byte sequential from relative to any channel, and memory management elements (RFM, TFM) for transferring data between said validation elements and said first RAM array relative to any channel in bit parallel byte sequential form;

said RL1 interfacing element in said receive pipeline operating on data bits received from said network relative to a channel configured for HDLC data communication to;

detect and remove bits inserted for transparency, collect bits to form bytes, remove bytes representing frame delimiting characters, and transfer remaining bytes sequentially to said RV element in the same pipeline;

said RV element operating relative to remaining received bytes in said HDLC data to;

perform CRC checking on said bytes and transfer said checked bytes to the RFM element in the same pipeline;

said RFM element operating to transfer said bytes relative to said HDLC channel into byte spaces in the respective data storage queue in said first RAM;

said TFM element in said transmit pipeline operating relative to any channel configured for HDLC communication to fetch data bytes sequentially from byte spaces in the respective data storage queue in said first RAM and to transfer said bytes sequentially to said TV element in the same pipeline;

said TV element operating relative to said HDLC channel for performing CRC checks thereon, transferring bytes sequentially to the TL1 element in the same pipeline, and generating and inserting reference CRC remainder characters into said transferred data;

said TL1 element operating relative to said HDLC channel to;

insert transparency bits, insert frame delimiting bytes, and transfer said data bit serially to said network in slots assigned to the respective channel; and

said first RAM unit has a data queue space relative to each slot for storing at least 4 bytes of data relative to the transmit pipeline and at least 4 bytes of data relative to the receive pipeline.

33. A DLC device in accordance with claim 32 including:

means in each of said elements constituting said receive and transmit pipelines for continuously manifesting indications of respective instantaneous processing states, and means in each of said pipeline elements for providing DONE indications during any time slot when the respective elements are in stable processing states suitable for terminating processing relative to the channel assigned to that slot and for later resuming processing relative to that channel;

a resource managing (RSM) element connected to said network, said first and second RAM arrays and said pipeline elements for directing the synchronous operations of said arrays and said pipeline elements relative to said network slots;

said RSM element comprising;

means coupled to said data communication network for receiving beginning of slot (BOS) signals indicating beginnings of slot periods at said network interface;

means responsive to said BOS signals for immediately retrieving configuration control (pre-CCR) information from said second RAM array indicating if the slot then beginning is assigned to an active channel, and subsequently retrieving additional configuration control (full CCR) information from said second array if the slot is assigned to an active channel;

means effective after receipt of said BOS signal for determining from previously retrieved full CCR information if the slot then ending is assigned to an active channel, and if it is sending end of slot (EOS) indications to each of said pipeline elements;

means responsive to DONE indications returned by said pipeline elements after said EOS indications for directing saving of respective pipeline element processing state indications in said second RAM array;

means responsive to said pre-CCR information indicating that the slot then beginning is assigned to an active channel for directing transfers of previously saved processing state information relative to that channel from said second RAM array to said pipeline elements; and

means operative after transferals of said previously saved state information for providing start indications to said pipeline elements for initiating processing relative to the channel to which the slot then beginning is assigned.

34. A DLC device according to claim 33 wherein:

said bit transfers at said data communication network interface during any slot are conducted during a short duration time portion of the respective slot such that most of the time in the respective slot is available to said RSM element and said pipeline elements for preparing for and carrying out said state saving and loading operations.