Apparatus for controlling access to a data bus

• US 5,218,681 A
• Filed: 08/31/1990
• Issued: 06/08/1993
• Est. Priority Date: 08/31/1990
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gephardt, Douglas D., MacDonald, James R.
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): CHUN, DEBRA
• Application Number:
  US07/576,061
• Time in Patent Office: 1,012 Days
• Field of Search: 395/325, 395/275, 395/725
• US Class Current: 710/300
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

An apparatus for use with a host computing system for controlling access to a first data bus which is external of the host computing system and which first data bus is operatively connected with a second data bus internal of the host computing system. The apparatus comprises a local processing unit which is configured substantially the same as the host processing unit and is driven by a separate local program distinct from the host processing program driving the host processing unit. The apparatus further comprises a supplemental processing circuit for processing information, which supplemental processing circuit is responsive to the host processing unit and to the local processing unit to determine whether the host processing unit or the local processing unit has operative access to the first data bus. In its preferred embodiment, the first data bus and the second data bus are operatively connected by a configurable buffer circuit for effecting data bus connection. Further, in the preferred embodiment of the present invention, the supplemental processing circuit generates an intervention signal in response to the local processing unit, the buffer circuit responding to the intervention signal by configuring appropriately to provide operative access by the apparatus of the second data bus.

Claims

1. An apparatus for use with a local computing system for coordinating control access by said local computing system to a host computing system;

said local computing system including a local processing unit and a local buffer unit operatively connected by a local internal system bus, said local buffer unit controlling communications access between an expansion bus and said local internal system bus;

said host computing system including a host processing unit and a host buffer unit operatively connected by a host internal system bus, said host buffer unit controlling communications access between said expansion bus and said host internal system bus;

the apparatus comprising;

an address register means for generating an address designation signal in response to an address designation input received from said local processing unit;

a mode designator means for generating a mode designation signal in response to a mode designation input received from said local processing unit;

an address comparing means for comparing said address designation signal with a currently addressed location signal received from said local processing unit, said currently addressed location signal indicating an address location addressed by said local processing unit during the extant clock cycle;

said address comparing means generating an address hit indication signal when said address designation signal is in a predetermined relationship with said currently addressed location signal;

a state designating means for establishing a current operating state for the apparatus in response to a mode designation input received from said mode designator means;

said state designating means being operatively connected with said host buffer unit;

said state designating means generating a host bus request signal to ascertain whether said host internal bus is available for control by said local processing unit in response to said address hit indication signal received from said address comparing means;

said host buffer unit generating a host bus acknowledge signal and operatively connecting said host internal bus with said expansion bus in response to said host bus request signal when said host internal bus is available for control by said local processing unit;

said state designating means generating an actuating signal in response to said host bus acknowledge signal, a portion of said actuating signal being state indicating signal, said local buffer unit operatively connecting said local internal bus with said expansion bus in response to said actuating signal;

said operative connection of said local internal bus with said expansion bus being effected in a predetermined configuration in response to said state indicating signal.

2. An apparatus for use with a local computing system for coordinating control access by said local computing system to a host computing system as recited in claim 1 wherein the apparatus is integrally formed with said local computing system.

3. An apparatus for use with a local computing system for coordinating control access by said local computing system to a host computing system as recited in claim 1 wherein said address comparing means receives an actuating signal from said mode designator means, said address comparing means responding to said actuating signal to generate said address hit indication signal only when said actuating signal has a predetermined value.

4. An apparatus for use with a local computing system for coordinating control access by said local computing system to a host computing system as recited in claim 1 wherein said state designating means receives an actuating signal from said mode designator means, said state designating means responding to said actuating signal to generate said intervention signal only when said actuating signal has a predetermined value.

5. An apparatus for use with a local computing system for coordinating control access by said local computing system to a host computing system as recited in claim 2 wherein said address comparing means receives an actuating signal from said mode designator means, said address comparing means responding to said actuating signal to generate said address hit indication signal only when said actuating signal has a predetermined value.

6. An apparatus for use with a local computing system for coordinating control access by said local computing system to a host computing system as recited in claim 2 wherein said state designating means receives an actuating signal from said mode designator means, said state designating means responding to said actuating signal to generate said intervention signal only when said actuating signal has a predetermined value.