Audio signal processing system having independent and distinct data buses for concurrently transferring audio signal data to provide acoustic control

• US 5,218,710 A
• Filed: 01/22/1990
• Issued: 06/08/1993
• Est. Priority Date: 06/19/1989
• Status: Expired due to Term

• Current Assignee: Pioneer Electronic Corporation (Pioneer Corporation)
• Original Assignee: Pioneer Electronic Corporation (Pioneer Corporation)
• Inventors: Naoe, Toshiyuki, Katsumura, Norimichi, Ishihara, Hiroyuki, Watanabe, Kazuo, Hayashi, Kazuhiro, Matsumoto, Yukio, Yamaki, Makio
• Primary Examiner(s): Anderson, Lawrence E.
• Assistant Examiner(s): Shah, Alpesh M.
• Application Number:
  US07/467,403
• Time in Patent Office: 1,233 Days
• Field of Search: 395/800, 395/425, 395/775, 381/36, 381/31, 381/61, 364/413
• US Class Current: 704/278
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: H03G 5/025 Equalizers; Volume or gain control in limited frequency bands

Abstract

An audio signal data processing system comprises input device for sequentially supplying an audio signal data, data memory control device for writing the audio signal data into a data memory and reading-out the data from the data memory, delay memory control device for sequentially reading-out the audio signal data from the data memory and storing the data into a location of a delay memory indicated by a writing address and for reading-out the audio signal data from a location of the delay memory indicated by a reading address and writing the data into the data memory, address designating devices for designating the writing and reading addresses, arithmetic device for multiplying a predetermined coefficient data to the audio signal data having been read-out by the delay memory control device and written into the data memory, and output device for providing the audio signal data in accordance with a result of operation by the arithmetic device. The data memory control device and the delay memory control device write and read the audio signal data into and from the data memory through data buses independent from each other.

Claims

1. An audio signal data processing system comprising:

first and second data buses;

a data memory coupled to said first and second data buses;

a delay memory coupled to said second data bus;

input means coupled to said first data bus for sequentially supplying an audio signal data;

data memory control means, coupled to said data memory, for writing said audio signal data into said data memory from said first data bus and reading-out the audio signal data from said data memory onto said first data bus and for reading-out said audio signal data from said data memory onto said second data bus for producing a delayed audio signal data and for writing said delayed audio signal data from said second data bus into said data memory;

delay memory control means, coupled to said delay memory, for storing the audio signal data from said second bus into a location of said delay memory indicated by a writing address, and for reading-out said audio signal data from a location of said delay memory indicated by a reading address onto said second data bus, thereby producing said delayed audio signal data;

a coefficient data memory for storing a predetermined coefficient data;

arithmetic means, coupled to said first data bus and said coefficient data memory, for multiplying said predetermined coefficient data by said audio signal data having been read-out from the data memory for producing acoustic control; and

output means, coupled to said first data bus, for providing the audio signal data in accordance with a result of operation of said arithmetic means, wherein said data memory control means writes and reads said audio signal data and said delayed audio signal data into and from said data memory respectively through a first data bus, and said second data bus, said first and second data buses being independent and distinct from each other.

2. An audio signal data processing system comprising:

first and second data buses independent and distinct from each other;

a data memory coupled to said first and second data buses;

a delay memory coupled to said second data bus;

input means coupled to said first data bus for sequentially supplying an audio signal data;

data memory control means, coupled to said data memory, for writing said audio signal data into said data memory from said first data bus and reading-out the audio signal data from said data memory onto said first data bus and for reading-out said audio signal data from said data memory onto said second data bus for producing a delayed audio signal data and for writing said delayed audio signal data from said second data bus into said data memory;

delay memory control means, coupled to said delay memory, for storing the audio signal data from said second bus into a location of said delay memory indicated by a writing address, and for reading-out said audio signal data from a location of said delay memory indicated by a reading address onto said second data bus, thereby producing said delayed audio signal data;

a coefficient data memory for storing a predetermined coefficient data;

arithmetic means, coupled to said first data bus and said coefficient data memory, for multiplying said predetermined coefficient data by said audio signal data having been read-out from the data memory for producing acoustic control; and

output means, coupled to said first data bus, for providing the audio signal data in accordance with a result of operation of said arithmetic means;

sequence control means coupled to said input means, said data memory control means, said delay memory control means, said arithmetic means and said output means for controlling operations of said input means, said data memory control means, said delay memory control means, said arithmetic means and said output means in accordance with a designated program; and

program setting means for supplying said designated program to said sequence control means and for initializing said data memory and said delay memory through said sequence control means whenever another program is designated.

3. An audio signal data processing system comprising:

first and second data buses independent and distinct from each other;

a data memory coupled to said first and second data buses;

a delay memory coupled to said second data bus;

input means coupled to said first data bus for sequentially supplying an audio signal data;

data memory control means, coupled to said data memory, for writing said audio signal data into said data memory from said first data bus and reading-out the audio signal data from said data memory onto said first data bus and for reading-out said audio signal data from said data memory onto said second data bus for producing a delayed audio signal data and for writing said delayed audio signal data from said second data bus into said data memory;

delay memory control means, coupled to said delay memory, for storing the audio signal data from said second bus into a location of said delay memory indicated by a writing address, and for reading-out said audio signal data from a location of said delay memory indicated by a reading address onto said second data bus, thereby producing said delayed audio signal data;

a coefficient data memory for storing a predetermined coefficient data;

arithmetic means, coupled to said first data bus and said coefficient data memory, for multiplying said predetermined coefficient data by said audio signal data having been read-out from the data memory for producing acoustic control; and

output means, coupled to said first data bus, for providing the audio signal data in accordance with a result of operation of said arithmetic means, wherein the data memory comprises at least two memory devices in which writing and reading operations of each memory device can be performed independently, and wherein said at least two memory devices are used independently whenever a processing operation using said delay memory is performed, and memory areas of said at least two memory devices are used as a consecutive memory area whenever a processing operation not using said delay memory is performed.

4. An audio signal data processing system comprising:

first and second data buses independent and distinct from each other;

a data memory coupled to said first and second data buses;

a delay memory coupled to said second data bus;

input means coupled to said first data bus for sequentially supplying an audio signal data;

data memory control means, coupled to said data memory, for writing said audio signal data into said data memory from said first data bus and reading-out the audio signal data from said data memory onto said first data bus and for reading-out said audio signal data from said data memory onto said second data bus for producing a delayed audio signal data and for writing said delayed audio signal data from said second data bus into said data memory;

delay memory control means, coupled to said delay memory, for storing the audio signal data from said second bus into a location of said delay memory indicated by a writing address, and for reading-out said audio signal data from a location of said delay memory indicated by a reading address onto said second data bus, thereby producing said delayed audio signal data;

delay time memory control means, coupled to said delay memory control means for writing a delay time data into a delay time memory and reading said delay time data to designate said reading address;

coefficient memory control means for writing a coefficient data into a coefficient memory and for reading the coefficient data;

arithmetic means, coupled to said first data bus and said coefficient memory, for multiplying said coefficient data read from said coefficient memory by said audio signal data having been read-out from said data memory for providing acoustic control, wherein the coefficient memory control means has a first transfer buffer for holding said coefficient data and for rewriting the coefficient data in said coefficient memory by transferring the coefficient data held in said first transfer buffer, and said delay time memory control means has a second transfer buffer for holding said delay time data and for rewriting the delay time data in said delay time memory by transferring said delay time data held in said second transfer buffer.