High temperature co-fired ceramic integrated phased array package

• US 5,219,377 A
• Filed: 08/10/1992
• Issued: 06/15/1993
• Est. Priority Date: 01/17/1992
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Poradish, Frank J.
• Primary Examiner(s): Echols, P. W.
• Assistant Examiner(s): Bryant, David P.
• Application Number:
  US07/927,893
• Time in Patent Office: 309 Days
• Field of Search: 29/830, 29/832, 29/840, 264/61, 333/247, 343/700 MS
• US Class Current: 29/830
• CPC Class Codes: H01Q 21/0087 Apparatus or processes specially adapted for manufacturing antenna arrays manufacturing waveguides H01P11/00
• CPC Class Codes: H01Q 23/00 Antennas with active circuits or circuit elements integrated within them or attached to them
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 by metal fusion

Abstract

A phased array package using a cofired ceramic material system to integrate antenna elements and an hermetic multi-chip MMIC cavity into a single module to provide incorporation of microwave circuit geometries into a system which has been used in the prior art only for low frequency applications. The integration provides a package very similar to a conventional integrated circuit package with substantial cost reductions over the complicated microwave assemblies of the present art.

Claims

1. A method of making an integrated package which comprises the steps of:

(a) providing a plurality of stacked layers, each layer comprising uniformly mixed fine particulate ceramic material and a binder in intimate relation with each other, including top and bottom layers and at least one intermediate layer therebetween, each of said layers having a pair of opposing major surfaces;

(b) disposing a radiating antenna element on a major surface of said at least one intermediate layer;

(c) providing at least one cavity, having a semiconductor chip therein, in one of said top, bottom, and intermediate layers;

(d) disposing metallization on a major surface of said at least one intermediate layer coupling said chip and said antenna element;

(e) providing vias extending through the major surfaces of said at least one intermediate layer having electrically conductive material therein for interconnection with a layer intimate with said intermediate layer; and

(f) cofiring said layers at a temperature of from about 1500°

C. to about 1800°

C. to remove said binder and cause sintering of said layers.

2. The method of claim 1 further including the step of forming metallized grooves in the side walls of said layers.

3. The method of claim 1 further including disposing metallization on a major surface of at least one of said top and bottom layers.

4. The method of claim 2 further including disposing metallization on a major surface of at least one of said top and bottom layers.

5. The method of claim 1 further including forming an interconnect at an edge portion of said intermediate layer coupled to said metallization.

6. The method of claim 2 further including forming an interconnect at an edge portion of said intermediate layer coupled to said metallization.

7. The method of claim 3 further including forming an interconnect at an edge portion of said intermediate layer coupled to said metallization disposed thereon.

8. The method of claim 4 further including forming an interconnect at an edge portion of said intermediate layer coupled to said metallization.

9. A method of making an integrated package which comprises the steps of:

(a) providing a plurality of stacked layers, each layer comprising uniformly mixed fine particulate ceramic material and a binder in intimate relation with each other, including top and bottom layers and at least one intermediate layer therebetween, each of said layers having a pair of opposing major surfaces;

(b) disposing a radiating antenna element on a major surface of said at least one intermediate layer;

(c) providing at least one cavity in one of said layers;

(d) disposing a semiconductor chip in said at least one cavity;

(e) disposing metallization on a major surface of said at least one intermediate layer coupling said chip and said antenna element;

(f) providing vias extending through the major surfaces of said at least one intermediate layer having electrically conductive material therein for interconnection with a layer intimate with said intermdiate layer; and

(g) cofiring said layers at a temperature of from about 1500°

C. to about 1800°

C. to remove said binder and cause sintering of said layers.