Method for manufacturing a semiconductor device including wafer aging, probe inspection, and feeding back the results of the inspection to the device fabrication process

• US 5,219,765 A
• Filed: 07/06/1990
• Issued: 06/15/1993
• Est. Priority Date: 09/12/1990
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Yoshida, Toru, Yorisaki, Shingo, Kaneda, Aizo, Ohomori, Isao, Mutoh, Masaaki, Matsumoto, Kunio, Kishimoto, Munehisa, Serizawa, Kooji, Sakaguchi, Suguru
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US07/549,069
• Time in Patent Office: 1,075 Days
• Field of Search: 437/8, 324/500, 324/158 R, 324/158 P, 324/158 T, 148/DIG. 162
• US Class Current: 438/10
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: Y10S 148/162 Testing steps
• CPC Class Codes: Y10S 438/975 Substrate or mask aligning feature

Abstract

The present invention provides a method for manufacturing a highly reliable semiconductor device without waste by incorporating predetermined functions into a wafer in a wafer completion process, aging the wafer in a wafer aging process, distinguishing between non-defective and defective chips in a probe inspection process, separating chips in the wafer one by one in a dicing process, sorting out the chips into non-defective and defective chips in a selection process, then analyzing failure information and feeding back the result of the analysis to the wafer completion process in a feedback process, thereby quickly analyzing and repairing a failure process on reliability in the wafer completion process.

Claims

1. A method for manufacturing a semiconductor device, including:

a wafer completion process comprising a plurality of processing steps for incorporating functions in a wafer, the wafer having a plurality of chips;

a wafer aging process for aging the wafer fabricated by said wafer completion process;

a probe inspection process for inspecting the functions of the wafer aged by said wafer aging process and distinguishing between non-defective and defective chips;

a dicing process for separating one by one the plurality of chips in the wafer inspected by said probe inspection process;

a selection process for sorting out the chips separated by said dicing process into non-defective and defective chips in accordance with a failure information provided from said probe inspection process; and

a feedback process for analyzing the failure information provided from said probe inspection process, estimating a cause failure and feeding back the result of the estimation of the cause of failure to said wafer completion process, wherein said feedback process includes a failure map making process for making a failure map in accordance with said failure information, and an analysis process for analyzing which processing steps in said wafer completion process causes a failure, on the basis of said failure map.

2. A method for manufacturing a semiconductor device according to claim 1, wherein said failure map making process is carried out for each failure mode.

3. A method for manufacturing a semiconductor device according to claim 1, wherein a plurality of wafers are formed in a production lot, and said failure map making process is carried out for each production lot.

4. A method for manufacturing a semiconductor device according to claim 1, wherein said analysis process analyzes a pattern of the failure map made by said failure map making process.

5. A method for manufacturing a semiconductor device according to claim 1, wherein in said wafer aging process a power source voltage and a signal voltage are supplied from power supplying electrodes for operating the chips in said wafer while suppressing noises using a noise suppressing multilayer ceramic chip capacitor.

6. A method for manufacturing a semiconductor device according to claim 5, wherein in said wafer aging process an electric current flowing through said power supplying electrodes is limited by a current limiting, thick or thin film resistor.

7. A method for manufacturing a semiconductor device according to claim 1, wherein in said wafer aging process, power supplying electrodes and an anisotropic electroconductive material are connected together electrically, and said anisotropic electroconductive material and the chips in said wafer are also connected together electrically, said anisotropic electroconductive material being interposed between the chips and the power supplying electrodes.

8. A method for manufacturing a semiconductor device according to claim 1, wherein in said wafer aging process, power supplying electrodes on a power supply board, and said chips of the wafer, are registered with each other, by the registration of (1) an alignment mark exposed through a hole in the power supply board and formed simultaneously with the power supplying electrodes on the power supply board having a plurality of said power supplying electrodes, with (2) an alignment mark formed on said wafer in said wafer completion process.

9. A method for manufacturing a semiconductor device according to claim 1, wherein in said wafer aging process, a plurality of said wafers and a plurality of power supply boards are stacked alternately, and a load is applied to all of said wafers and said power supply boards at a same time.

10. A method for manufacturing a semiconductor device according to claim 9, wherein said load is applied to the plurality of said wafers and the plurality of power supply boards while the plurality of wafers and the plurality of power supply boards are stacked alternatively, the load being applied in a direction in which the plurality of said wafers and the plurality of power supply boards are stacked alternatively.

11. A method for manufacturing a semiconductor device according to claim 1, wherein in said wafer aging process, said wafer and a power supply board are put one upon the other in a container having a pressure block, then the internal gas of said container is discharged, and due to a pressure difference between the atmospheric pressure and the internal pressure of said container, said pressure block is pressed against said wafer or said power supply board to make electrical conduction between the chips in said wafer and power supplying electrodes of said power supply board.

14. A method for manufacturing a semiconductor device according to claim 2, wherein a plurality of wafers are formed in a production lot, and said failure map making process is carried out for each production lot.

12. A method for manufacturing a semiconductor device, including:

a wafer completion process comprising a plurality of processing steps for incorporating functions in a wafer, the wafer having a plurality of chips;

a wafer aging process for aging the wafer fabricated by said wafer completion process, inspecting the functions of the wafer and distinguishing between non-defective and defective chips;

a probe inspection process for inspecting the functions of the wafer aged by said wafer aging process and distinguishing between non-defective and defective chips;

a dicing process for separating one by one the plurality of chips in the wafer inspected by said probe inspection process;

a selection process for sorting out the chips separated by said dicing process into non-defective and defective chips in accordance with a failure information provided from said wafer aging process and that provided from said probe inspection process; and

a feedback process for analyzing the failure information provided from said wafer aging process and that provided from said probe inspection process, estimating a cause of failure and feeding back the result of the estimation of the cause of failure to said wafer completion process, wherein said feedback process includes a failure map making process for making a failure map in accordance with said failure information, and an analysis process for analyzing which processing steps in said wafer completion process causes a failure, on the basis of said failure map.

13. A method for manufacturing a semiconductor device according to claim 12, wherein said failure map making process is carried out for each failure mode.

15. A method for manufacturing a semiconductor device according to claim 12, wherein said analysis process analyzes a pattern of the failure map made by said failure map making process.

16. A method for manufacturing a semiconductor device according to claim 12, wherein in said wafer aging process a power source voltage and a signal voltage are supplied from power supplying electrodes for operating the chips in said wafer while suppressing noises using a noise suppressing multilayer ceramic chip capacitor.

17. A method for manufacturing a semiconductor device according to claim 16, wherein in said wafer aging process an electric current flowing through said power supplying electrodes is limited by a current limiting, thick or thin film resistor.

18. A method for manufacturing a semiconductor device according to claim 12, wherein in said wafer aging process, power supplying electrodes and an anisotropic electroconductive material are connected together electrically, and said anisotropic electroconductive material and the chips in said wafer are also connected together electrically, said anisotropic electroconductive material being interposed between the chips and the power supplying electrodes.

19. A method for manufacturing a semiconductor device according to claim 12, wherein in said wafer aging process, power supplying electrodes on a power supply board, and said chips in the wafer, are registered with each other, by the registration of (1) an alignment mark exposed through a through hole in the power supply board and formed simultaneously with the power supplying electrodes on the power supply board having a plurality of said power supplying electrodes, with (2) an alignment mark formed on said wafer in said wafer completion process.

20. A method for manufacturing a semiconductor device according to claim 12, wherein in said wafer aging process, a plurality of said wafers and a plurality of power supply boards are stacked alternately, and a load is applied to all of said wafers and said power supply boards at a same time.

21. A method for manufacturing a semiconductor device according to claim 20, wherein said load is applied to the plurality of said wafers and the plurality of power supply boards while the plurality of wafers and the plurality of power supply boards are stacked alternatively, the load being applied in a direction in which the plurality of said wafers and the plurality of power supply boards are stacked alternatively.

22. A method for manufacturing a semiconductor device according to claim 12, wherein in said wafer aging process, said wafer and a power supply board are put one upon the other in a container having a pressure block, then the internal gas of said container is discharged, and due to a pressure difference between the atmospheric pressure and the internal pressure of said container, said pressure block is pressed against said wafer or said power supply board to make electrical conduction between the chips in said wafer and power supplying electrodes of said power supply board.