Digital-to-analog converter with improved performance and method therefor

• US 5,220,326 A
• Filed: 03/30/1992
• Issued: 06/15/1993
• Est. Priority Date: 03/30/1992
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Irwin, James S., Ledzius, Robert C., Manvar, Dhirajlal N.
• Primary Examiner(s): Logan, Sharon D.
• Application Number:
  US07/860,663
• Time in Patent Office: 442 Days
• Field of Search: 341/143, 341/118, 341/144, 341/152, 341/120, 375/27, 375/28
• US Class Current: 341/118
• CPC Class Codes: H03M 3/358 of non-linear distortion, e.g. instability avoiding instability by structural design H03M3/44
• CPC Class Codes: H03M 3/51 Automatic control for modifying converter range

Abstract

A digital-to-analog converter (20) with improved performance includes an offset/scaler (23), a sigma-delta modulator (25), and an analog summing network (26). In one embodiment, the offset/scaler (23) scales an input signal by a predetermined amount, such as three-quarters, to compensate for nonlinearities in a transfer characteristic of the sigma-delta modulator (25). In another embodiment, the sigma-delta modulator (25) is a sufficiently-resolved sigma-delta modulator. The offset/scaler (23) provides an offset to the sufficiently-resolved sigma-delta modulator (25) sufficient to force a coarse bit thereof into an idle pattern.

Claims

1. A digital-to-analog converter with improved performance comprising:

a scaler having an input coupled for receiving a first digital signal, and an output for providing said first digital signal scaled by a predetermined amount;

a sigma-delta modulator having an input coupled to said scaler, and an output for providing a second digital signal; and

an analog summing network having inputs for receiving respective bits of said second digital signal, and an output for providing an analog signal of the digital-to-analog converter;

said predetermined amount greater than or equal to a loss of dynamic range of said sigma-delta modulator.

2. The digital-to-analog converter of claim 1 wherein said predetermined amount is equal to three-quarters.

3. The digital-to-analog converter of claim 1 wherein said sigma-delta modulator is characterized as having an order higher than one.

4. A digital-to-analog converter with improved performance comprising:

an offset circuit having an input for receiving a first digital signal, and an output for providing a second digital signal, said second digital signal offset by a predetermined amount from said first digital signal;

a sigma-delta modulator having an input for receiving said second digital signal, and an output for providing a third digital signal; and

an analog summing network having inputs for receiving respective ones of a plurality of bits of said third digital signal, and an output for providing an analog output signal of the digital-to-analog converter;

said sigma-delta modulator characterized as being a sufficiently-resolved sigma-delta modulator;

said predetermined amount sufficient to ensure that a coarse bit of said sigma-delta modulator goes into an idle pattern.

5. The digital-to-analog converter of claim 4 wherein said predetermined amount is substantially equal to one-half of a trim bit of said sigma-delta modulator.

6. The digital-to-analog converter of claim 4 wherein said sigma-delta modulator provides a most significant bit as said coarse bit.

7. The digital-to-analog converter of claim 4 wherein said sigma-delta modulator provides said most significant bit and a second bit which is not said most significant bit or a second most significant bit as feedback bits of said sigma-delta modulator.

8. The digital-to-analog converter of claim 4 wherein said third digital signal includes said coarse bit, said second bit, and at least one bit which is less significant than said second bit.

9. A method of improving performance of a digital-to-analog converter comprising the steps of:

receiving a first digital signal at an input of said digital-to-analog converter;

adding said first digital signal to one-half of said first digital signal to provide a second digital signal;

left-shifting said second digital signal to provide a third digital signal;

providing said third digital signal to an input of a sigma-delta modulator;

coupling an output of said sigma-delta modulator to an input of an analog summing network;

providing an output of said analog summing network as an output of said digital-to-analog converter.

10. The method of claim 9 further comprising the step of offsetting said third digital signal by a predetermined offset before providing said third digital signal to said sigma-delta modulator.

11. The method of claim 10 wherein said step of providing said third digital signal further comprises the step of providing said third digital signal to an input of a sufficiently-resolved sigma-delta modulator.

12. The method of claim 11 wherein said step of offsetting said third digital signal further comprises the step of offsetting said third digital signal by an amount sufficient to ensure that a coarse bit of said sufficiently-resolved sigma-delta modulator goes into an idle pattern.

13. A digital-to-analog converter with improved performance comprising:

input means for receiving a first digital signal;

an offset/scaler having an input coupled to said input means, and an output, for offsetting said digital signal by a first predetermined amount and for scaling said digital signal by a second predetermined amount to provide a second digital signal at said output;

a sigma-delta modulator having an input coupled to said output of said offset/scaler, and an output for providing a third digital signal; and

an analog summing network having an input for receiving said third digital signal, and an output for providing an analog output signal of the digital-to-analog converter;

said sigma-delta modulator characterized as being a sufficiently-resolved sigma-delta modulator;

said first predetermined amount greater than or equal to a loss of dynamic range of said sigma-delta modulator;

said second predetermined amount insuring a coarse bit of said sigma-delta modulator goes into an idle pattern.

14. The digital-to-analog converter of claim 13 wherein said second predetermined amount is substantially equal to one-half of a trim bit of said sigma-delta modulator.