Monopulse reply extractor for SSR navigation systems

• US 5,220,329 A
• Filed: 07/30/1991
• Issued: 06/15/1993
• Est. Priority Date: 07/30/1991
• Status: Expired due to Term

• Current Assignee: Cardion Newco Incorporated (Thales SA)
• Original Assignee: Cardion, Inc.
• Inventors: Verbeke, Charles E. Jr., Stein, Robert H.
• Primary Examiner(s): Sotomayor, John B.
• Application Number:
  US07/738,045
• Time in Patent Office: 686 Days
• Field of Search: 342/40, 342/39, 342/32, 342/37, 342/159
• US Class Current: 342/40
• CPC Class Codes: G01S 13/784 Coders or decoders therefor; Degarbling systems; Defruiting systems

Abstract

An SSR reply decoding system for separating pulse codes of a series of closely-spaced or overlapping SSR replies is disclosed. A delay line is connected to receive pulses representing the leading edge of each SSR reply code pulse. The delay line has a length corresponding to at least two bracket lengths of an SSR reply. A bracket decoder is connected to respective taps of the delay line for determining the beginning and end of a first SSR reply. A phantom reply detector is connected to the remaining taps for inhibiting the bracket decoder when two replies are represented by pulses in the delay lines, one of the replies having a pulse space from the pulse of another reply equal to a framing pulse period for an SSR reply. The phantom reply detector therefore inhibits the detection of phantom replies. As a discriminate for determining when pulses having the spacing of a framing period belong to different replies, azimuth data is provided which will permit discrimination of these phantom conditions.

Claims

1. An SSR processor/decoder for separating pulse code replies in a series of replies comprising:

a leading edge detector for receiving said series of replies and generating pulses representing the leading edge of each pulse in said replies;

a delay line connected to receive said pulses representing said leading edge, said delay line having a plurality of taps corresponding to pulses having a known time position within a reply, first and second of said taps corresponding to first and second framing pulses representing the first and last pulses in a reply, a third tap representing a time position following said first framing pulse between a pair of consecutive pulses, and fourth and fifth taps which represent time positions subsequent to said first framing pulse, and which differ by the time interval between framing pulses;

a bracket decoder connected to said first and second taps for determining the beginning and end of a reply;

a phantom reply detector connected to said third, fourth and fifth taps for inhibiting said bracket decoder when two replies are represented by pulses in said delay line, one of said replies having a pulse spaced from a pulse of said other reply equal to the spacing of said framing pulses; and

code pulses position decoder means for receiving said pulses from said delay line, and a signal from said bracket decoder, said code pulse position decoder providing data representing a single reply.

2. The SSR processor/decoder of claim 1 wherein said phantom reply detector receives an additional signal representing the direction of each reply pulse, and compares said direction of each reply pulse with a reference direction representing the direction of said first framing pulse to determine the identity of said two pulses from different replies.

3. The SSR processor/decoder of claim 2 wherein said third tap correspond to a time position following said first framing pulse an before a first code pulse position, and said fourth tap corresponds to a time position which differs with respect to said third tap by the time difference between said known framing pulses, and a fifth tap corresponding to a time difference with respect to said fourth tap corresponding to said known framing pulses time difference.

4. The SSR processor/decoder of claim 1 wherein said phantom reply detector includes a state machine which determines whether said two replies are overlapped, producing a garbled condition, or are closely spaced non-overlapping replies.

5. The SSR processor/decoder of claim 4 wherein said state machine identifies the framing pulse position of a later occurring closely spaced reply, and releases said bracket decoder inhibit when a first reply passes through said delay line.

6. The SSR processor/decoder of claim 4 wherein said state machine identifies said garble condition and releases said inhibit when a second later reply first framing pulse reaches said first tap.

7. A device for processing SSR transponder replies, which include a serial pulse stream identified by first and second framing pulses, said device establishing the beginning and end of overlapping and closely spaced replies comprising:

a leading edge detector for generating a pulse stream having pulses which occur synchronously with pulses of said serial data stream;

delay line for receiving said leading edge detector pulse stream, said delay line having a plurality of taps which can identify the presence or absence of pulses occurring in said pulse stream;

a bracket decoder connected to first and second of said taps for identifying said first and second framing pulses, whereby the beginning and end of a reply is detected; and

,

a phantom reply detector connected to third, G'"'"', and fourth, GF1, remaining taps, and to a source of data identifying the position in azimuth of each of said code pulses corresponding to each of said leading edge pulses, said phantom reply detector inhibiting said bracket decoder when said third and fourth taps produce simultaneously occurring pulses, indicating the presence of a second overlapping reply, and releasing said inhibit when said third tap produces a pulse representing a corresponding code pulse having a different position in azimuth than a previously detected framing pulse.

8. The device of claim 7, wherein said phantom reply detector includes a fifth, GF2, remaining tap, said fifth remaining tap and said fourth remaining tap indicating the presence of two closely-spaced non-overlapping replies, said phantom reply detector inhibiting said bracket decoder until said leading edge pulses corresponding to first and second framing pulses of an earlier reply exit said delay line.

9. The system of claim 8 further comprising a decoder means for receiving reply pulses from said delay line which occur between framing pulses identified by said bracket decoder, said decoder receiving said source of data for indicating said azimuth position of each of said reply pulses and comparing said position with a reference position of a framing pulse belonging to said reply pulses, said decoder providing a confidence level indication of each reply pulse based on said azimuth data.

10. The system of claim 9 further comprising:

means for summing each pulse azimuth position which lies within a window azimuth position; and

,

means for computing an average azimuth position from said sum.

11. A device for processing and decoding SSR transponder replies comprising:

a delay line for storing at least two transponder replies;

a bracket detector connected to said delay line for indicating the presence of framing pulses spaced apart a framing time interval;

a data bus supplying position data identifying the relative azimuth direction of each pulse of said transponder replies;

a decoder connected to said bracket detector, data bus and delay line, said decoder including;

an azimuth position window memory for receiving reference azimuth data and defining a range of positions;

means for determining when a pulse has been received which lies within said range of positions; and

,

means for generating a confidence indication for each pulse based on whether or not said pulse lies within said rang of positions.

12. The device for processing and decoding of claim 11 further comprising means for forming an average of the azimuth positions which lie within said range.

13. The device for processing and decoding of claim 12 further comprising means for updating a transponder position with said average position.

14. A device for processing SSR transponder replies which include a serial pulse stream identified by first and second framing pulses, said device establishing the beginning and end of overlapping and closely spaced relies comprising:

a delay line for receiving a stream of pulses representing said serial pulse stream, said delay line having a plurality of taps which can identify the presence or absence of pulses within said data stream;

position determining means for providing data identifying the relative position of each pulse passing through said delay line with respect to a reference position;

a bracket decoder connected to said delay line for detecting first and second pulses in said delay line spaced in time equal to the spacing of said framing pulses; and

,

a phantom reply detector connected to said taps and said position determining means, said phantom reply detector determining from the relative position of pulses in said delay line and said data identifying the relative position of each pulse the presence of overlapping and adjacent replies, said phantom reply detector supplying an inhibit signal to said bracket decoder to prevent detection of a phantom reply identified by a pair of pulses from different relies having the spacing of two framing pulses.

15. The device of claim 14 wherein said position determining means establishes a reference position equal to

16. The device of claim 14 wherein said phantom reply detector is connected to a tap for sensing a pulse which occurs between the first framing pulse of a reply and the next adjacent pulse position in said reply.

17. The device of claim 16 wherein said phantom reply detector is connected to two additional taps for sensing a pulse which occurs one framing period and two framing periods, respectively, from said pulse which occurs between the first framing pulse and said next adjacent position.