Method and apparatus for preventing overerasure in a flash cell

• US 5,220,533 A
• Filed: 11/06/1991
• Issued: 06/15/1993
• Est. Priority Date: 11/06/1991
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Turner, John E.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Nguyen, Tan
• Application Number:
  US07/788,607
• Time in Patent Office: 587 Days
• Field of Search: 365/218, 365/184, 365/185, 365/900
• US Class Current: 365/185.3
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing

Abstract

A method and apparatus for erasing Flash EPROM cells that avoids overerasure is provided. A high-impedance device is placed between the drain of the cell and the high-voltage supply used to erase the cell. As soon as the cell enters the onset of depletion and begins to conduct, most of the high voltage is dropped across the high-impedance device, leaving insufficient potential across the cell for Fowler-Nordheim tunneling to continue. The erase process is thus self-limiting. The process can be used on a chain or array of EPROM cells, with erasure stopping when any one of the cells conducts. Bias differences between erase and read modes assure that the cell that first goes into depletion is not in depletion in normal operation.

Claims

1. A method of erasing a programmed Flash cell and stopping erasure of said cell on onset of conduction by said cell, said cell having a gate, a source, a drain and a floating gate from which charge must be removed by placing a high potential difference thereacross to erase the cell, said method comprising:

applying ground potential to said gate;

applying ground potential to said source; and

applying a high positive potential to said drain through a high-impedance device connected to said drain;

wherein;

said high positive potential causes electrons to flow off said floating gate to said drain and through said high-impedance device, such that when enough electrons have been removed from said floating gate;

said cell begins to conduct, and

current flows through said high-impedance device and said cell and drops most of said high potential across said high-impedance device, insufficient potential remaining across said floating gate to remove additional electrons, whereby erasure is stopped at onset of conduction by said cell.

2. A method of erasing a chain of Flash cells and stopping erasure of said chain of cells on onset of conduction by any cell in said chain, each of said cells having a gate, a source, a drain and a floating gate from which charge must be removed by placing a high potential difference thereacross to erase the cell, the sources of all cells in said chain being connected in common to a source line and the drains of all cells in said chain being connected in common to a drain line, all of said cells being programmed, said method comprising:

applying ground potential to each of said gates;

applying ground potential to said source line; and

applying a high positive potential to said drain line through a high-impedance device connected to said drain line;

wherein;

said high positive potential causes electrons to flow off said floating gates to said drain line and through said high-impedance device, such that when enough electrons have been removed from said floating gate of one of said cells;

said one of said cells begins to conduct, and

current flows through said high-impedance device and said cell and drops most of said high potential across said high-impedance device, insufficient potential remaining across said floating gates to remove additional electrons, whereby erasure is stopped at onset of conduction by said cell.

3. A method of erasing an array of Flash cells and stopping erasure of said array of cells on onset of conduction by any cell in said array, each of said cells having a gate, a source, a drain and a floating gate from which charge must be removed by placing a high potential difference thereacross to erase the cell, said cells connected in parallel chains, the sources of all cells in each said chain being connected in common to a respective source line for said chain and the drains of all cells in each said chain being connected in common to a respective drain line for said chain, all of said cells being programmed, said method comprising:

connecting together said respective drain lines as a common drain line;

applying ground potential to each of said gates;

applying ground potential to said source lines; and

applying a high positive potential to said common drain line through a high-impedance device connected to said common drain line;

wherein;

said high positive potential causes electrons to flow off said floating gates to said common drain line and through said high-impedance device, such that when enough electrons have been removed from said floating gate of one of said cells;

said one of said cells begins to conduct, and

current flows through said high-impedance device and said cell and drops most of said high potential across said high-impedance device, insufficient potential remaining across said floating gates to remove additional electrons, whereby erasure is stopped at onset of conduction by said cell.

4. The method of claim 3 wherein said step of applying ground potential to said source lines comprises:

connecting together said respective source lines as a common source line; and

applying ground potential to said common source line.

5. Apparatus for erasing a programmed Flash cell and for stopping erasure of said cell on onset of conduction by said cell, said cell having a gate, a source, a drain and a floating gate from which charge must be removed by placing a high potential difference thereacross to erase the cell, said apparatus comprising:

means for applying ground potential to said gate;

means for applying ground potential to said source;

high-impedance means for attaching to said drain; and

means for applying a high positive potential to said high-impedance means connected to said drain;

wherein;

said high positive potential causes electrons to flow off said floating gate to said drain and through said high-impedance device, such that when enough electrons have been removed from said floating gate;

said cell begins to conduct, and

current flows through said high-impedance device and said cell and drops most of said high potential across said high-impedance means, insufficient potential remaining across said floating gate to remove additional electrons, whereby erasure is stopped at onset of conduction by said cell.

6. The apparatus of claim 5 wherein said high-impedance means comprises a high-resistance resistor.

7. The apparatus of claim 5 wherein said high-impedance means comprise a transistor.

8. The apparatus of claim 5 wherein said high-impedance means comprises a capacitive pumped circuit.

9. The apparatus of claim 8 wherein said capacitive pumped circuit comprises an oscillator.

10. Apparatus for erasing a chain of Flash cells and for stopping erasure of said chain of cells on onset of conduction by any cell in said chain, each of said cells having a gate, a source, a drain and a floating gate from which charge must be removed by placing a high potential difference thereacross to erase the cell, the sources of all cells in said chain being connected in common to a source line and the drains of all cells in said chain being connected in common to a drain line, all of said cells being programmed, said apparatus comprising:

means for applying ground potential to each of said gates;

means for applying ground potential to said source line of said chain;

high-impedance means for attaching to said drain line; and

means for applying a high positive potential to said drain line through high-impedance means connected to said drain line;

wherein;

said high positive potential causes electrons to flow off said floating gates to said drain line and through said high-impedance device, such that when enough electrons have been removed from said floating gate of one of said cells;

said one of said cells begins to conduct, and

current flows through said high-impedance device and said cell and drops most of said high potential across said high-impedance device, insufficient potential remaining across said floating gates to remove additional electrons, whereby erasure is stopped at onset of conduction by said cell.

11. The apparatus of claim 10 wherein said high-impedance means comprises a high-resistance resistor.

12. The apparatus of claim 10 wherein said high-impedance means comprises a transistor.

13. The apparatus of claim 10 wherein said high-impedance means comprises a capacitive pumped circuit.

14. The apparatus of claim 13 wherein said capacitive pumped circuit comprises an oscillator.

15. Apparatus for era sing an array of Flash cells and for stopping erasure of said array of cells on onset of conduction by any cell in said array, each of said cells having a gate, a source, a drain and a floating gate from which charge must be removed by placing a high potential difference thereacross to erase the cell, said cells connected in parallel chains, the sources of all cells in each said chain being connected in common to a respective source line for said chain and the drains of all cells in each said chain being connected in common to a respective drain line for said chain, all of said cells being programmed, said apparatus comprising:

means for connecting together said respective drain lines as a common drain line;

means for applying ground potential to each of said gates;

means for applying ground potential to said source lines;

high-impedance means for attaching to said common drain line; and

means for applying a high positive potential to said common drain line through said high-impedance means connected to said common drain line;

wherein;

said high positive potential causes electrons to flow off said floating gates to said common drain line and through said high-impedance device, such that when enough electrons have been removed from said floating gate of one of said cells;

said one of said cells begins to conduct, and

current flows through said high-impedance device and said cell and drops most of said high potential across said high-impedance device, insufficient potential remaining across said floating gates to remove additional electrons, whereby erasure is stopped at onset of conduction by said cell.

16. The apparatus of claim 15 wherein said high-impedance means comprises a high-resistance resistor.

17. The apparatus of claim 15 wherein said high-impedance means comprise a transistor.

18. The apparatus of claim 15 wherein said high-impedance means comprises a capacitive pumped circuit.

19. The apparatus of claim 18 wherein said capacitive pumped circuit comprises an oscillator.

20. The apparatus of claim 15 wherein said means for applying ground potential to said source lines comprises:

means for connecting together said respective source lines as a common source line; and

means for applying ground potential to said common source line.