Data transfer between high bit rate buses via unshielded low bit rate bus

• US 5,220,561 A
• Filed: 06/20/1990
• Issued: 06/15/1993
• Est. Priority Date: 06/20/1990
• Status: Expired due to Fees

• Current Assignee: Zarlink Semiconductor Inc. (Microchip Technology Incorporated)
• Original Assignee: Zarlink Semiconductor Inc. (Microchip Technology Incorporated)
• Inventors: Brennan, Robert P., Servant, Gordon W., Nuhn, Derek J., Jeffrey, George A.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): MARCELO, MELVIN C
• Application Number:
  US07/541,050
• Time in Patent Office: 1,091 Days
• Field of Search: 370/84, 370/105.1, 370/84, 375/121, 375/122
• US Class Current: 370/545
• CPC Class Codes: H04J 3/0626 plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
• CPC Class Codes: H04M 1/253 Telephone sets using digital voice transmission
• CPC Class Codes: H04Q 11/0442 Exchange access circuits
• CPC Class Codes: H04Q 11/0471 Terminal access circuits
• CPC Class Codes: H04Q 2213/216 Code signals; Framing (not synchronizing)
• CPC Class Codes: H04Q 2213/297 Coupling circuits between different (rate) TDM systems

Abstract

A method and apparatus for transferring high data rate data between a pair of separated high data rate buses comprising storing a group of high data rate data from one of the buses, one of which is connected to a digital telephone set, reading the stored data at a low data rate, conditioning the low data rate data to remove high frequency components therefrom, applying the conditioned data to an unshielded cable for transmission to the separated other high data rate bus, receiving and storing the conditioned data from the unshielded cable and reading the stored conditioned data at a high data rate to said other bus.

Claims

1. Data transfer means between a digital telephone set, a first high bit rate serial data bus and plural peripherals comprising:

(a) means for outwardly transmitting low data rate data between the telephone set and the peripherals on a low data rate bus and for receiving low data rate data from the low data rate bus,

(b) a first converter connected to the high data bus for converting high bit rate incoming data signals carried by the high bit rate data bus to said low bit rate signals for said outward transmission and for converting received low bit rate data signals to high bit rate signals for outward high bit rate transmission on the high but rate data bus,

(c) at least one second converter, at a peripheral, for converting low bit rate incoming data signals to high bit rate outgoing data signals and high bit rate incoming data signals to low bit rate outgoing data signals,

each of said converters comprising;

(i) first and second shift registers each having capacity of a data frame,

(ii) means for writing incoming data from a high data rate bus connected thereto into the first shift register during a high data rate frame time interval at a high bit rate,

(iii) means for reading the data stored in the first shift register onto a low data bus for outward transmission during a low data rate frame time interval at a low bit rate,

(iv) means for writing incoming data from the low rate bus into the second shift register during the interval when data stored in the first shift register is being read,

(v) means for reading data from the second shift register to the high data rate bus connected thereto during the interval when data stored in the first shift register is being written,

(vi) means for providing a separate high bit rate clock signal for each converter,

(vii) means for providing a low bit rate clock signal for each converter,

(viii) means for clocking both first and second shift registers of each converter using the high bit rate clock signal during said high data rate frame time interval, and

(ix) means for clocking both first and second shift registers of each converter using the low bit rate clock signal during said low data rate frame time interval,

(x) the clocking intervals of the low and high bit rate clock signals in each converter alternating with each other,

whereby said data is transmitted frame by frame between high data rate data buses connected to the telephone set and said peripheral but along the low data rate data bus between the telephone set and said at least one peripheral,

(xi) and further including means for applying a low data rate clock signal from the first converter to the low data rate bus, and means at each second converter for receiving the low bit rate clock signal and providing a frame synchronizing signal on the high data rate bus connected thereto.

2. Data transfer means as defined in claim 1 further comprising means for conditioning data signals prior to being applied to the low data rate bus, to limit the high frequency components therefrom.

3. Data transfer means between a digital telephone set, a first high rate serial data bus and plural peripherals comprising:

(a) means for outwardly transmitting low data rate data between the telephone set and the peripherals on a low data rate bus and for receiving low data rate data from the low data rate bus,

(b) a first converter connected to the high data bus for converting high bit rate incoming data signals carried by the high bit rate data bus to said low bit rate signals for said outward transmission and for converting received low bit rate data signals to high bit rate signals for outward high bit rate transmission on the high bit rate data bus,

(c) at least one second converter, at a peripheral, for converting low bit rate incoming data signals to high bit rate outgoing data signals and high bit rate incoming data signal to low bit rate outgoing data signals,

each of said converters comprising;

(i) first and second shift registers each having capacity of a data frame,

(ii) means for writing incoming data from a high data rate bus connected thereto into the first shift register during a high data rate frame time interval at a high bit rate,

(iii) means for reading the data stored in the first shift register onto a low data bus for outward transmission during a low data rate frame time interval at a low bit rate,

(iv) means for writing incoming data from the low rate bus into the second shift register during the interval when data stored in the first shift register is being read,

(v) means for reading data from the second shift register to the high data rate bus connected thereto during the interval when data stored in the first shift register is being written,

(vi) means for providing a separate high bit rate clock signal for each converter,

(vii) means for providing a low bit rate clock signal for each converter,

(viii) means for clocking both first and second shift registers of each converter using the high bit rate clock signal during said high data rate frame time interval, and

(ix) means for clocking both first and second shift registers of each converter using the low bit rate clock signal during said low data rate frame time interval,

(x) the clocking intervals of the low and high bit rate clock signals in each converter alternating with each other,

whereby said data is transmitted frame by frame between high data rate data buses connected to the telephone set and said peripheral but along the low data rate data bus between the telephone set and said at least one peripheral,

(xi) and further including means for applying a low data rate clock signal from the first converter to the low data rate bus, and means in each second converter for receiving the low bit rate clock signal from the low bit rate bus and for synchronizing its shift registers to a frame of data words defined by the low bit rate clock signal.

4. Data transfer means as defined in claim 3 in which the low data rate bus is an unshielded cable.

5. Data transfer means as defined in claim 3 in which the low bit rate clock is derived from the telephone set.

6. Data transfer means comprising:

(a) first and second shift registers having similar capacities,

(b) means for writing incoming data from a first high data rate bus into the first shift register during a first predetermined time interval, at a high bit rate,

(c) means for reading the data stored in the first shift register onto a low data rate bus for outward transmission during a second predetermined time interval at a low bit rate,

(d) means for writing incoming data from the low data rate bus into the second shift register during the interval when data stored in the first shift register is being read,

(e) means for reading outgoing data from the second shift register to the first high data rate bus during the interval when data stored in the first shift register is being written,

(f) means for providing a high bit rate clock signal,

(g) means for providing a low bit rate clock signal,

(h) means for clocking both first and second shift registers using the high bit rate clock signal during said first predetermined time interval,

(i) means for clocking both first and second shift registers using the low bit rate clock signal during said second predetermined time interval,

(j) the clocking intervals of the low and high bit rate clock signals alternating with each other,

(k) a second converter at a remote peripheral, the second converter being connected to a second high data rate bus and to the low data rate bus, comprising;

(i) a third shift register having similar capacity as the first shift register,

(ii) means for writing incoming data from the low data rate bus into the third shift register,

(iii) means for reading data from the third shift register to the second high data rate bus,

(iv) means for providing a high bit rate clock signal,

(v) means for providing a low bit rate clock signal,

(vi) means for enabling the third shift register to write data and for clocking the third shift register with the low bit rate clock during said writing,

(vii) means for subsequently enabling the third shift register to read data and for clocking the third shift register with the high bit rate clock,

(viii) a fourth shaft register having similar capacity as the third shift register,

(ix) means for writing incoming data from the second high data rate bus into the fourth shift register,

(x) means for reading data from the fourth shift register to the low data rate bus,

(xi) means for enabling the fourth shift register to write data from the second high data rate bus and for clocking the fourth shift register with the high bit rate clock during said writing and during the clocking interval of the third shift register with the high bit rate clock,

(xii) means for enabling the fourth shift register to read data to the low data rate bus and for clocking the fourth shift register during said reading and during the clocking interval of the third shift register with the low bit rate clock,

whereby the third and fourth shift registers are clocked together and respectively read from and write to the low data rate bus during a similar time interval and respectively read from and write to the second high data rate bus during a second similar time interval,

(l) means for conditioning data signals prior to being applied to the low data rate bus, to limit the high frequency components thereof, and

(m) means for applying a low data rate synchronizing signal to the low data rate bus, and means at the second converter for receiving said synchronizing signal and for synchronizing the third and fourth shift registers to frames of words defined by said synchronizing signal.