Method of fabricating a thin film transistor having a silicon carbide buffer layer

• US 5,221,631 A
• Filed: 03/15/1991
• Issued: 06/22/1993
• Est. Priority Date: 02/17/1989
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Shimada, Osamu, Murakami, Takahiro, Uchida, Teruo, Ikeda, Hiroyuki
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US07/669,425
• Time in Patent Office: 830 Days
• Field of Search: 148/DIG. 148, 437/101, 437/100, 437/40, 437/41, 357/23.7, 357/4
• US Class Current: 438/158
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

A method of making a thin film transistor is described incorporating the steps of forming a gate electrode, a layer of insulating material, a layer of buffer material, a layer of semiconductor material, a source electrode and drain electrode. The invention reduces the problem of variation in threshold voltage of thin film transistors due to external stress such as the gate voltage or temperature.

Claims

1. A method of forming a thin film transistor comprising the steps of:

forming a gate electrode on an insulating substrate, forming a first layer of insulating material over said gate electrode, forming a second layer of buffer material over said first layer, forming a third layer of semiconductor material over said second layer, forming a source electrode on said third layer, and forming a drain electrode spaced apart from said source electrode on said third layer, said step of forming a second layer includes the step of selecting a buffer material having a carrier density higher than the carrier density of said semiconductor material and the step of separating said second layer into two sections, each said section spaced apart from the other, one said section formed below said source electrode and the other said section formed below said drain electrode.

2. The method of claim 1 wherein said step of forming a second layer includes the step of forming a second layer of molybdenum.

3. The method of claim 2 wherein said step of forming a second layer includes the step of etching the surface of said molybdenum layer.

4. The method of claim 3 wherein said step of etching includes the step of etching with a sputtering device.

5. The method of claim 1 wherein said step of forming a second layer includes the step of forming a second layer with thickness of about 300 angstroms.

6. The method of claim 1 wherein said step of forming a third layer includes the step of forming an amorphous silicon layer.