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Bitwise implementation mechanism for a circuit design synthesis procedure

  • US 5,222,029 A
  • Filed: 12/08/1992
  • Issued: 06/22/1993
  • Est. Priority Date: 09/12/1986
  • Status: Expired due to Term
First Claim
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1. A method of creating a plurality of bit-level model instances from higher level model instances for synthesizing circuit designs, the higher level model instances having at least one multi-bit port for receiving at least one multi-bit signal, the bit-level and higher level model instances being stored in a memory of a data processing system, the method comprising the steps of:

  • selecting for execution in the data processing system a rule having a consequence portion containing a macrorule, the macrorule being executed by the data processing system over a selected one of the bits of the multi-bit signal received by the multi-bit port;

    executing in the data processing system a function of the selected macrorule for the selected one bit of the multi-bit signal in order to create a first one of the bit-level model instances; and

    repeating in the data processing system the steps of the selecting and executing the macrorule over a succeeding bit of the multi-bit signal using the preceding one of the bit level model instances to create a subsequent bit-level model instance.

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