Sequence generator
First Claim
1. An improved sequence generator for use with a source of successive bits of random data, said improved sequence generator comprising:
- shift register means for storing said bits of data, said shift register means having a feedback loop;
switch means for selecting between said source means, in a first mode of operation, and said feedback loop, in a second mode of operation, for input to said shift register means; and
control logic means for switching said switch means from said second mode to said first mode as said source means provides a each successive bit of random data.
2 Assignments
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Accused Products
Abstract
An improved sequence generator. The inventive generator (10) is adapted for use with a source (12) for providing successive bits of random data. The invention (10) includes a shift register (18) with a feedback loop. The shift register (18) stores bits of random data. Input to the shift register (18) is determined by a switch (16) which selects between the random data source (12), in a first mode of operation, and the feedback loop, in a second mode of operation. A control logic circuit (20) triggers the switch from the second mode to the first mode, for one clock cycle, as the random data source (12) provides a each successive bit of random data. Thus, optimum performance is obtained without the need to gate clock signals or to control the operation of the shift register.
21 Citations
26 Claims
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1. An improved sequence generator for use with a source of successive bits of random data, said improved sequence generator comprising:
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shift register means for storing said bits of data, said shift register means having a feedback loop; switch means for selecting between said source means, in a first mode of operation, and said feedback loop, in a second mode of operation, for input to said shift register means; and control logic means for switching said switch means from said second mode to said first mode as said source means provides a each successive bit of random data. - View Dependent Claims (2, 3, 4, 5)
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6. An improved sequence generator for use with an encryption system comprising:
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source means for providing successive bits of random data; shift register means for storing said bits of data, said shift register means having a feedback loop, said shift register means including a shift register consisting essentially of cascaded flip-flop circuits; switch means for selecting between said source means, in a first mode of operation, and said feedback loop, in a second mode of operation, for input to said shift register means; first function means disposed in said feedback loop for providing a function of the data bits stored in said shift register; second function means for providing a function of the output of said source means and the output of said first function means; and control logic means for switching said switch means from said second mode to said first mode as said source means provides a each successive bit of random data, said control logic means switching switch means between the output of said first function means in said second mode to the output of said second function means in said first mode.
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7. An improved method of randomizing an encryption circuit including the steps of:
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providing successive bits of random data; storing the bits of random data in a shift register having a feedback loop; selecting either the bits of random data, in a first mode of operation, or the feedback loop, in a second mode of operation, for input to the shift register; and selecting the first mode of operation as each successive bit of random data is provided and otherwise operating in said second mode. - View Dependent Claims (8, 9)
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10. A sequence generator for use with a source of successive bits of random data, said sequence generator comprising:
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a shift register for storing said bits of random data, said shift register having a feedback loop; a switch for selecting between said random data source in a first mode of operation, and said feedback loop, in a second mode of operation, for input to said shift register; control logic for switching said switch between said second mode and said first mode; and an output port for providing a sequence of bits from the contents of said shift register. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A method of generating a sequence of bits including the steps of:
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providing successive bits of random data to an input port of a shift register, said shift register having a feedback loop; selecting either said bits of random data, in a first mode of operation, or said feedback loop, in a second mode of operation, for input from said input port to said shift register; operating in said first mode of operation as each successive bit of random data is provided and otherwise operating in said second mode; providing a sequence of bits at an output port of said shift register by sequentially providing the bits stored in said shift register. - View Dependent Claims (23, 24, 25, 26)
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Specification