Fakeout method and circuitry for displays

• US 5,222,212 A
• Filed: 11/13/1990
• Issued: 06/22/1993
• Est. Priority Date: 09/16/1988
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Chips and Technologies, Inc. (Intel Corporation)
• Inventors: Oguchi, Tetsuji, Johary, Arun
• Primary Examiner(s): Nguyen, Phu K.
• Application Number:
  US07/614,056
• Time in Patent Office: 952 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/518, 364/521, 364/522, 340/758, 340/785, 340/771, 340/716, 340/717, 395/162, 395/153, 395/154
• US Class Current: 345/520
• CPC Class Codes: G06F 3/1475 with conversion of CRT control signals to flat panel control signals, e.g. adapting the palette memory

Abstract

A video display controller capable of providing video control information for either a flat panel or a CRT display. The controller includes a plurality of main circuits, alternate circuits, select circuits, and a circuit for identifying the display device used in the system. Each main circuit receives information from the processor and generates main video information compatible with a CRT. Each alternate circuit receives information from the processor and generates alternate video information compatible with a flat panel display. Each select circuit receives main and alternate video information and outputs main video information when the display device is a CRT display and the alternate video information when the display device is a flat panel display. In one embodiment, the alternate circuits are programmable registers. In another embodiment, tables are used to program the alternate registers to provide compatibility for a number of possible display devices.

Claims

1. In a data processing system capable of operating in a plurality of predefined display modes, the system having a processor, a video display device of a type that is one of a plurality of types of video display devices, a memory for storing video display information, and a video controller for receiving input from the processor and for interacting with said memory to provide video information to the display device, a controller comprising:

a plurality of main circuits corresponding to the plurality of display modes, each capable of storing main video information for a first type of display device, each of the main circuits generating main video information for a respective one of the plurality of display modes;

a plurality of alternate circuits, each alternate circuit capable of storing alternate video information for a second type of video display device, each of the alternate circuits storing alternate video information for a respective one of the plurality of display modes, the alternate video information being stored only when the value of the main video information is different in value from the alternate video information;

a plurality of select circuit means, said plurality of select circuit means for receiving main video information when a first type of display means is operational, and receiving main video information and alternate video information when a display device of a second type is operational;

means for receiving an identification signal from the video display device, which signal indicates to the controller which of the plurality of types of video display devices is coupled to the controller, each of said select circuit means being responsive to the identification signal, said select circuit means providing main video information to the video display device when the first type of display device is coupled to the processor and providing main video information and alternate video information when the second type of display device is coupled to the controller, the alternate video information only being provided when the value of the main video information is different from the value of the alternate video information differs from said main video information;

a plurality of programming tables, each corresponding to a display device; and

means for decoding the identification signal from the video display device to enable the one of said programming tables which corresponds to the identified video display device, said programming tables providing alternate video function information to the alternate registers during system initialization, said alternate video function information differing from said main video function information in at least those registers required for the selected display mode.

2. The controller of claim 1 and wherein at least one of said alternate circuits is programmable.

3. The controller of claim 1 and wherein at least one of said alternate circuits is programmed by said processor during powerup of said system.

4. The controller of claim 1 and wherein said video information includes at least one of the following:

horizontal line size, vertical line size, blinking, blink rate, sync functions, and clock functions.

5. The controller of claim 1 and wherein at least one of said main circuits comprises a register.

6. The controller of claim 1 and wherein at least one of said alternate circuits comprises a register.

7. The controller of claim 1 wherein the first predetermined video display device is a cathode ray tube ("CRT") and the second predetermined video display device is a flat plane display.

8. The controller of claim 7 wherein said means for receiving an identification signal from said display device to generate display identification information comprises

a plurality of main registers coupled to said processor for receiving an input from said processor and for generating main video information for the first video display device, said main video information enabling the video display device to operate in one of the predefined display modes;

alternate registers coupled to said processor for receiving an input from said processor and for generating alternate video information for the second video display device, the contents of said alternate registers differing from the contents of the main registers and enabling the second video display device to display video information in the same predefined display mode as the main registers; and

select circuit means coupled to said main and said alternate registers and responsive to information from said processor identifying said display device to generate said display identification information, said display identification information comprising said main video function information when said display device is said first display device and said identification information comprising said alternate video function information when said alternate video information for the predefined display modes differs from said main video function information.

9. The controller of claim 1 wherein at least one of said alternate circuits is programmed by said processor during a reset operation for resetting system parameters.