High performance communications interface for multiplexing a plurality of computers to a high performance point to point communications bus

• US 5,222,216 A
• Filed: 07/12/1991
• Issued: 06/22/1993
• Est. Priority Date: 07/12/1991
• Status: Expired due to Fees

• Current Assignee: TM Patents LP
• Original Assignee: Thinking Machines Corporation (Oracle Corporation)
• Inventors: Moser, Thomas J., Doolittle, Robert A., Parish, Edward C., Gillett, Sharon E., Satterfield, David L., Nesheim, William A., Tardiff, James P.
• Primary Examiner(s): RICHARDSON, ROBERT
• Application Number:
  US07/729,429
• Time in Patent Office: 711 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2, 395/275, 395/325, 395/800, 395/550
• US Class Current: 710/310
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A high performance communications interface device for connecting a high speed computer to a high performance communications bus. The high performance communications interface device includes a high performance communications interface device processor, a source interface, a destination interface and at least one I/O processor which controls the transfer of data to the high speed computer from the high performance communications bus and from the high speed computer to the high performance communications bus.

Claims

1. A high performance communication interface for transferring data between at least one external device and a high performance communication bus, said high performance communication interface comprising:

a first data transfer bus;

a second data transfer bus;

at least one IO processor interface in electrical communication with said at least one external device and in electrical communication with said first data transfer bus and said second data transfer bus;

a destination communication interface in electrical communication with said high performance communication bus and comprising a destination data fifo and a destination event controller, said destination communication interface capable of receiving data into said destination data fifo from said high performance communication bus and transmitting data from said destination data fifo over said first data transfer bus to said at least one IO processor interface in response to events queued in said destination event controller; and

a source communication interface in electrical communication with said high performance communication bus and comprising a source data fifo and a source event controller, said source communication interface capable of receiving data into said source data fifo from said at least one IO processor interface over said second data transfer bus and transmitting data from said source data fifo to said high performance communication bus in response to events queued in said source event controller,

wherein said events are queued in said destination event controller in response to occurrences in said destination communication interface and said events are queued in said source event controller in response to occurrences in said source communication interface.

2. The high performance communication interface of claim 1 further comprising a high performance communication interface controller in electrical communication with said at least one IO processor interface, said high performance communication interface controller controlling the flow of data between said first data transfer bus and said at least one IO processor interface and controlling the flow of data between said second data transfer bus and said at least one IO processor interface in response to commands from said external device.

3. The high performance communication interface of claim 2 wherein said high performance communication interface controller is in electrical communication with said source communication interface and said destination communication interface, said high performance communication interface controller queuing events in said event controller of said source communication interface and queuing events in said event controller of said destination communication interface to thereby control the flow of data between said source communication interface and said high performance communication bus and to thereby control the flow of data between said high performance communication bus and said destination communication interface, respectively, in response to commands from said external device.

4. The high performance communication interface of claim 1 further comprising a first clock signal having a first clock frequency and a second clock signal having a second clock frequency, said second clock frequency being greater than said first clock frequency, said flow of data between first data transfer bus and said at least one IO processor interface and said flow of data between said second data transfer bus and said at least one IO processor interface being clocked by said first clock signal and said execution of commands by said at least one IO processor interface being clocked by said second clock signal.

5. The high performance communication interface of claim 4 wherein said second clock frequency is an integer multiple of said first clock frequency.

6. The high performance communication interface of claim 1 wherein said at least one IO processor interface comprises:

an IO data input fifo in electrical communication between said at least one external device and said second data transfer bus; and

an IO data input controller,

said IO data input fifo receiving from said at least one external device and transmitting data to said second data transfer bus in response to commands from said IO data input controller.

7. The high performance communication interface of claim 6 wherein said at least one IO processor interface further comprises a second data transfer bus interface in electrical communication between said second data transfer bus and said IO data input fifo, and in electrical communication with said IO data input controller, said second data transfer bus interface permitting the flow of data between said second data transfer bus and said IO data input fifo in response to commands from said IO data input controller.

8. The high performance communication interface of claim 6 wherein said at least one IO processor interface further comprises an external bus communication interface in electrical communication between said at least one external device and said IO data input fifo, said external bus communication interface receiving data from said IO data input fifo and transmitting data to said at least one external device.

9. The high performance communication interface of claim 1 wherein said at least one IO processor interface comprises:

an IO data output fifo in electrical communication between said at least one external device and said first data transfer bus; and

an IO data output controller,

said IO data output fifo receiving data from said first data transfer bus and transmitting data to said at least one external device in response to commands from said IO data output controller.

10. The high performance communication interface of claim 9 wherein said at least one IO processor interface further comprises a first data transfer bus interface in electrical communication between said first data transfer bus and said IO data output fifo, and in electrical communication with said IO data output controller, said first data transfer bus interface permitting the flow of data between said first data transfer bus and said IO data output fifo in response to commands from said IO data output controller.

11. The high performance communication interface of claim 10 wherein said at least one IO processor interface further comprises an external bus communication interface in electrical communication between said at least one external device and said IO data output fifo, said external bus communication interface receiving data from said at least one external device and transmitting data to said IO data output fifo.

12. An IO processor interface for use in a high performance communication interface having a first data transfer bus, a second data transfer bus and a high performance communication interface controller, said IO processor interface comprising:

an IO data output controller in electrical communication with said high performance communication interface controller;

a first data bus interface in electrical communication with sad first data transfer bus and in electrical communication with said IO data output controller;

an IO data output fifo in electrical communication said first data bus interface;

an IO data input controller in electrical communication with said high performance communication interface controller;

a second data bus interface in electrical communication with a second data transfer bus and in electrical communication with said IO data input controller; and

an IO data input fifo in electrical communication said second data bus interface,

said first data bus interface transmitting data to said IO data output fifo from said first data bus in response to commands from said IO data output controller, said commands received by said IO data output controller from said high performance communication interface controller,

said second data bus interface transmitting data from said IO data output fifo to said second data bus in response to commands from said IO data input controller, said commands received by said IO data input controller from said high performance communication interface controller.

13. A communication interface for use in a high performance communication interface, said communication interface in electrical communication with said high performance communication bus and a data transfer bus, said communication interface comprising:

a data fifo; and

an event controller,

said communication interface capable of transferring data between said data fifo and at least one IO processor interface over said data transfer bus, and capable of transmitting data between said data fifo and said high performance communication bus in response to events queued in said event controller,

said events being queued in said event controller in response to occurrences in said communication interface.

14. A high performance communication interface controller for use in a high performance communication interface,

said high performance communication interface controller in electrical communication with a source communication interface in electrical communication with a high performance communication bus, said source communication interface comprising a source communication interface event controller, and

said high performance communication interface controller in electrical communication with a destination communication interface in electrical communication with said high performance communication bus, said destination communication interface comprising a destination communication interface event controller,

said high performance communication interface controller entering events in said source communication interface event controller and entering events in said destination communication interface event controller to thereby control the flow of data between said source communication interface and said high performance communication bus and to thereby control the flow of data between said high performance communication bus and said destination communication interface, respectively, in response to commands from an external device.

15. A high performance communication interface for transferring data between at least one external device and a high performance communication bus, said high performance communication interface comprising:

a first data transfer bus;

a second data transfer bus;

at least one IO processor interface in electrical communication with said at least one external device and in electrical communication with said first data transfer bus and said second data transfer bus; and

a communication interface in electrical communication with said high performance communication bus and comprising;

a destination data fifo and a destination event controller, said communication interface capable of receiving data into said destination data fifo from said high performance communication bus and transmitting data from said destination data fifo over said first data transfer bus to said at least one IO processor interface in response to events queued in said destination event controller; and

a source data fifo and a source event controller, said communication interface capable of receiving data into said source data fifo from said at least one IO processor interface over said second data transfer bus and transmitting data from said source data fifo to said high performance communication bus in response to events queued in said source event controller,

wherein said events are queued in said destination event controller and in said source event controller in response to occurrences in said communication interface.

16. A processor device comprising:

a bus;

a processor in communication with said bus, said processor executing instructions for performing operations on data transferred over said bus;

a first clock signal having a first clock frequency; and

a second clock signal having a second clock frequency less than said first clock frequency,

said execution of instructions by said processor being clocked by said first clock signal, and said transfer of data over said bus being clocked by said second clock signal.

17. The processor device of claim 16 wherein said first clock frequency is an integer multiple of said second clock frequency.