Pipeline computer system having write order preservation

• US 5,222,219 A
• Filed: 08/27/1990
• Issued: 06/22/1993
• Est. Priority Date: 10/25/1988
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Company (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Kline, Mark, Bahr, Richard G., Stumpf, Bernard, Kurtze, Jeffrey D.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): AN, MENG AI T
• Application Number:
  US07/574,389
• Time in Patent Office: 1,030 Days
• Field of Search: 395/375, 395/325, 395/575
• US Class Current: 710/105
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/4213 with asynchronous protocol

Abstract

A method for preserving data transfer order in a pipeline computer system, wherein a first block of data is transferred from a first device to at least a second device during a first computer cycle. Simultaneously, the first block of data is stored within the first device. Druing a second computer cycle, a second block of data is transferred from the first device to the second device, and an acknowledge signal is issued, indicating the success or failure of the transfer of the first block of data. If the acknowledge signal indicates a failed data transfer, a reject signal is issued and data transfer is restarted beginning with the previously failed data transaction which has been stored within the first device, and data transfer then continues with a preserved data transfer order.

Claims

1. A data transfer method with write order preservation for a pipeline computer system having at least first and second devices coupled by a shared communication bus, and capable of performing data transfer operations over a plurality of computer cycles, comprising the steps of:

securing access to the shared communication bus by a first device;

transferring a first set of data from said first device to a second device during a first computer cycle;

storing within said first device, said first set of data;

transferring a second set of data from said first device to said second device druing a third or subsequent computer cycle;

issuing a reject signal during said third or subsequent computer cycle by said first device, to be received by at least said second device, said reject signal indicating that said first set of data is to be ignored;

ignoring by at least said second device of said first set of data transferred during said first computer cycle in response to receipt of said reject signal issued by said first device; and

re-transferring from said first device to said second device, said first set of data stored in said first device in response to said first device issuing said reject signal.

2. The method of claim 1, including, after the step of storing the first set of transferred data, the steps of:

releasing access of the bus by said first device after transferring said first set of data; and

reaccessing the bus by the first device before transferring said second set of data.

3. The method of claim 1, wherein additional devices are connected to the bus and receive data transferred thereon, further including the step of:

receiving said reject signal by said additional devices, said reject signal indicating that the first set of data transmitted from said first device was incorrect; and

ignoring, by said additional devices, of said first set of data transferred during said first computer cycle in response to receipt of said reject signal issued by said first device.

4. The method of claim 1 wherein transferring said first and second sets of data includes transferring device operation commands for controlling an operation to be perrformed by said second device.

5. The method of claim 4 wherein transferring said device operation commands includes transferring write operation commands.

6. The method of claim 1 further including generally simultaneously with the step of transferring said second set of data by said frist device, the step of sending an acknowledge signal from said second device to said first device during said third or subsequent computer cycle.

7. The method of claim 6 wherein said acknowledge signal indicates that the first set of data was not properly received by said second device.

8. The method of claim 7 wherein said reject signal is issued by said first device in response to receipt of said acknowledge signal indicating that the first set of data was not properly received by said second device.

9. The method of claim 1 wherein issuing said reject signal by said first device to be received by at least said second device indicates that said first set of data transmitted from said first device was incorrect.

10. The method of claim 1 further including after the step of transferring a second set of data, the steps of:

not issuing a reject signal during said subsequent computer cycle by said first device, indicating that said first or subsequent set of data is not to be ignored;

transferring a third set of data from said first device to a second device during a given computer cycle;

storing within said first device, said third set of data;

transferring a fourth set of data from said first device to said second device during a computer cycle subsequent to said given computer cycle; and

returing to the step of not issuing a reject signal during a subsequent computer cycle indicating said subsequent set of data is not to be ignored.

11. A data transfer method with write order preservation for a pipeline computer system having at least first and second devices coupled by a shared communication bus, and capable of performing data transfer operations over a plurality of computer cycles, comprising the steps of:

securing access to the bus by a first device;

transferring a first set of data from said first device to a second device during a first computer cycle;

storing within said first device, said first set of data until successful transfer of said first set of data to said second device is adknowledged by said second device;

transferring a second set of data from said first device to said second device during a third computer cycle;

sending an acknowledge signal by said second device to said first device during said third computer cycle indicating that said first set of data was not properly received by said second device;

issuing a reject signal by said first device to be received by at least said second device in response to said acknowledge signal, indicating said first set of data was not properly received;

ignoring by at least said second device, of said first set of data transferred during said first computer cycle, in response to receipt of said reject signal issued by said first device; and

re-transferring from said first device to said second device in a computer cycle subsequent to said third cycle, said first set of data stored in said first device in response to said first device issuing said reject signal.

12. A data transfer method with write order preservation for a pipeline computer system having at least first and second devices coupled by a shared communication bus, and capable of performing data write operations over a plurality of computer cycles, comprising the steps of:

securing access to the bus by a first device;

transferring a first write command from said first device to a second device during a first computer cycle;

storing within said first device, said previously transferred write command;

transferring a second write command from said first device to said second device during a third or subsequent computer cycle;

sending an acknowledge signal by said second device to said first device during said third or subsequent computer cycle, indicating that said first write command was not properly received by said second device;

issuing a reject signal during said third or subsequent computer cycle by said first device, to be received by said second device, indicating that the write command transmitted from said first device during a first computer cycle was not properly received;

ignoring by at least said second device, of said first write command transferred during said first computer cycle, in response to receipt of said reject signal issued by said first device; and

re-transferring said first write command stored in said first device from said first device to said second device, in response to said first device issuing said reject signal.