Process and apparatus for reducing power usage microprocessor devices operating from stored energy sources

• US 5,222,239 A
• Filed: 09/30/1992
• Issued: 06/22/1993
• Est. Priority Date: 07/28/1989
• Status: Expired due to Term

• Current Assignee: FMC Technologies Incorporated (TechnipFMC, plc), Wichita Falls Power Management LLC
• Original Assignee: Michael H. Davis
• Inventors: Rosch, Winn L.
• Primary Examiner(s): CHAN, EDDIE P
• Application Number:
  US07/954,706
• Time in Patent Office: 265 Days
• Field of Search: 395/750, 364/707, 365/227, 455/343
• US Class Current: 713/322
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 11/3423 where the assessed time is active or idle time
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A process and apparatus for preparing said process for reducing the power consumption of microprocessor-based devices by reducing the frequency of the oscillator governing the logical operation of the microprocessor during periods of use in which system performance is not critical. In one embodiment of apparatus the microprocessor is controlled by a monitor circuit operable with the microprocessor and operated by the variable frequency oscillator. In another embodiment a hardware monitor circuit is utilized and which tracks microprocessor instructions to determine periods of use when performance is not critical. The shift in oscillator speed is mediated by a flip-flop latch circuit connected between one or more clock oscillators and the oscillator input of the controlled microprocessor.

Claims

1. A process for automatically reducing the power usage of a microprocessor comprising the steps of:

(a) continuously generating monitor interrupt signals for monitoring the operations of the microprocessor at predetermined intervals of time;

(b) searching within an instruction stream of the microprocessor for a plurality of instructions executed by the microprocessor upon the occurrence each of of said monitor interrupt signals by means of a monitoring circuit;

(c) comparing said plurality of searched instructions with a predefined list of instructions stored in memory to determine when at least one of said searched instructions constitutes a predefined instruction; and

(d) supplying at least a first operation frequency to said microprocessor upon the occurrence of said predefined instruction, and a reduced second operation frequency to said microprocessor upon the non-occurrence of said predefined instruction, wherein the power usage of said microprocessor is reduced according to the occurrence or non-occurrence of said predefined instruction by reduction of the operation frequency supplied to said microprocessor.

2. A process as in claim 1, wherein

said step of searching comprises evaluation of a predetermined number of instructions in an instruction stream both forwardly and backwardly from a starting address in said instruction stream.

3. A process as in claim 1, wherein

said step of comparing comprises the determination of whether at least one of said searched instructions is a critical instruction which would require critical performance of said microprocessor.

4. A process as in claim 3, wherein

said predefined list of instructions comprises critical instructions wherein said at least one searched instruction is critical if it matches one of said list of instructions.

5. A process as in claim 4, wherein

said list of critical instructions constitute instructions utilized in operation of said microprocessor for which performance is critical.

6. A process as in claim 3, wherein

said critical instruction constitutes an interrupt other than said monitor interrupt indicating that critical usage of said microprocessor is necessary.

7. A process as in claim 1, wherein

said step of comparing comprises the determination of whether said at least one of said searched instructions is a non-critical instruction which would not require critical performance of said microprocessor.

8. A process as in claim 1, wherein

said step of comparing comprises incrementing an inactivity counter upon no pre-defined instruction occurring in said plurality of searched instructions, and upon the occurrence of a predetermined value for said inactivity counter said second operation frequency will be supplied to said microprocessor.

9. A process as in claim 1, wherein

said step of supplying said first or second operation frequencies includes the determination of whether operation of the microprocessor is presently at said first or second operation frequencies which is the operation frequency to be supplied wherein an inactivity counter will be reset, or whether said microprocessor is operating at said first or second operation frequencies with the other of said operation frequencies to be supplied to then supply said other operation frequency to said microprocessor and then reset said inactivity counter.

10. A process as in claim 1, wherein

said step of searching comprises evaluation of a predetermined number of instructions in an instruction stream, and said step of making a determination comprises determining whether said searched instructions constitute a predefined sequence of instructions.

11. A process to reduce the power usage of a microprocessor utilizing a stored energy power source comprising the steps of:

continuously generating monitor interrupt signals from a system in which a microprocessor operates to initiate monitoring operations at predetermined intervals of time,

said monitoring operation being performed by means of a circuit for monitoring operation of said microprocessor, and comprising the searching of a plurality of instructions executed by said microprocessor upon the occurrence of each of said monitor interrupt signals in at least one direction in an instruction stream from a predetermined starting address in said instruction stream,

determining whether any of the instructions searched constitutes a pre-defined instruction,

supplying at least a first oscillation frequency to said microprocessor upon the occurrence of said pre-defined instruction, and

supplying at least one second oscillation frequency to said microprocessor upon no pre-defined instruction occurring in said plurality of instructions wherein said at least one second oscillation frequency is lower than said first oscillation frequency such that the power usage of said microprocessor will be reduced by supplying said second oscillation frequency depending upon the non-occurrence of said pre-defined instruction.

12. An apparatus for reducing the power usage of a microprocessor utilizing a stored energy power source comprising,

as microprocessor having means for continuously generating monitor interrupt signals at predetermined intervals of time;

a monitoring circuit means for monitoring instructions executed by said microprocessor upon the occurrence of each of said monitor interrupt signals, and including means to compare said plurality of instructions which are monitored by said monitoring circuit means to instructions stored in memory,

a latch circuit means having an input thereof coupled to the output of said monitoring circuit means,

at least the source of an oscillating frequency for generating at least two discrete frequencies, coupled to said input of said latch circuit, wherein the output of said latch circuit couples a selected one of said at least two frequencies to said microprocessor upon the occurrence of at least one of said monitored instructions with at least one instruction in said stored instructions to enable the reduction of power usage dependent upon said selected one of said frequencies utilized in said microprocessor operation.

13. An apparatus as in claim 12, wherein

said monitoring circuit means comprises a portion of said microprocessor wherein said monitoring of instructions executed by said microprocessor is accomplished by control program information supplied to said monitoring circuit means.

14. An apparatus as in claim 13, wherein

said program information is stored in memory associated with said microprocessor.

15. An apparatus as in claim 13, wherein

said program information is stored in an external memory coupled with said monitoring circuit means for access thereto.

16. An apparatus as in claim 12, wherein

said monitoring circuit means comprises a separate circuit associated with said microprocessor being provided with program information to enable monitoring of said instructions executed by said microprocessor.

17. An apparatus as in claim 12, wherein

said monitoring circuit means is an external circuit coupled with said microprocessor and having program stored in memory means associated therewith for monitoring said instructions executed by said microprocessor.

18. An apparatus as in claim 12, wherein

said monitoring circuit means is coupled to an address bus of said microprocessor and monitors the instructions executed by said microprocessor on said address bus.

19. An apparatus as in claim 12, wherein

said means to compare said instructions executed by said microprocessor includes a list of instructions stored in memory to which said monitored instructions are compared to determine which of said at least two frequencies will be coupled to said microprocessor for operation thereof.