Logic placement using positionally asymmetrical partitioning algorithm

• US 5,224,056 A
• Filed: 10/30/1991
• Issued: 06/29/1993
• Est. Priority Date: 10/30/1991
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Chene, Mon R., Trimberger, Stephen M.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US07/784,844
• Time in Patent Office: 608 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/121
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A modified partitioning method for placement of a circuit design into a programmable integrated circuit device (PICD), the PICD having a specific distribution of physical resources corresponding to a specific circuit structure. The circuit design includes a plurality of circuit elements which include specific circuit elements which correspond to the specific circuit structure. The modified method includes the steps of identifying the specific circuit elements and partitioning the plurality of circuit elements such that the identified specific circuit elements are placed in a location corresponding to the specific physical distribution of resources. In one embodiment of the modified partitioning method according to the present invention, the step of partitioning further includes the steps of forming into a cell the identified specific circuit elements and performing a first phase of partitioning wherein the cell and the remaining ones of the plurality of circuit elements are partitioned into successively smaller groups until a stop condition is satisfied. The cell is then decomposed such that the contents of the group containing the cell change to include the specific circuit elements. The group containing the specific circuit elements is then partitioned such that the area and the location of the group corresponds to the specific physical distribution of resources.

Claims

1. A partitioning method for placement of a circuit design into a programmable integrated circuit device having a specific distribution of physical resources, the circuit design comprising a plurality of circuit elements, the method comprising:

identifying from the plurality of circuit elements specific circuit elements which have a relationship with each other, the relationship to be implemented by the specific physical distribution of resources;

forming into a cell the identified specific circuit elements, thereby leaving as remaining elements all elements of the plurality of circuit elements other than the specific circuit elements;

partitioning the cell and remaining elements until a stop condition is satisfied, the cell being partitioned into a group when the stop condition is satisfied;

decomposing the cell such that the group contains the specific circuit elements of the corresponding cell; and

partitioning the decomposed group containing the specific circuit elements such that the locations of the specific circuit elements correspond to the specific physical distribution of resources.

2. A method according to claim 1 wherein a first area and a first location of the group are defined by an X-range value and an orthogonal Y-range value, and the step of decomposing further includes adjusting the X-range value and the Y-range such that the group is associated with a second area and a second location corresponding to the specific physical distribution of resources.

3. A method according to claim 2 wherein the step of adjusting includes constricting the Y-range and expanding the X-range such that the first area and the first location of the group form a horizontal strip corresponding to the specific physical distribution of resources.

4. A method according to claim 3 wherein partitioning includes the division of the plurality of circuits by means of horizontal and vertical partitioning lines, and the step of partitioning the group containing the specific circuit elements further comprises limiting partitioning to vertical partitioning lines.

5. A method according to claim 1 wherein the stop condition, associated with the step of partitioning the cell and the remaining elements, is satisfied when the cell is separated from all remaining elements.

6. A method of establishing a placement of logic elements into a logic array comprising the steps of:

a. grouping logic elements which have a specified relationship to each other into a cell;

b. placing said cell and all remaining logic elements by a partitioning process;

c. ungrouping said cell into specified logic elements and marking said specified logic elements with a constraint; and

d. further partitioning said specified logic elements and said remaining logic elements, said elements marked with said constraint being partitioned according to said constraint.

7. A method of establishing placement as in claim 6 in which said partitioning process comprises a min-cut partitioning process.

8. A method of establishing placement as in claim 7 in which said constraint comprises limiting partitioning of said specified logic elements marked with said constraint to be partitioned by a vertical line only.

9. A method of establishing suggested placement as in claim 7 in which said further partitioning uses a process other than said min-cut process.

10. A method of establishing placement as in claim 6 in which said step of ungrouping said cell occurs after said cell has been partitioned into a group having none of said remaining logic elements.