Arrangement method for logic cells in semiconductor IC device

• US 5,224,057 A
• Filed: 10/09/1992
• Issued: 06/29/1993
• Est. Priority Date: 02/28/1989
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kora, Kaori, Igarashi, Mutsunori
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US07/959,468
• Time in Patent Office: 263 Days
• Field of Search: 364/491, 364/490, 364/489, 364/488
• US Class Current: 716/123
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

An arrangement method for logic cells in a semiconductor IC device, in which a plurality of logic cells are arranged on a semiconductor chip and wiring is performed between the logic cells so as to realize a desired circuit, comprises the steps of developing the logic cell informations to be arranged on the chip and already-arranged cell and wiring informations into connection pins and inhibited areas for wiring, converting the inhibited areas for wiring into equivalent pins so as to treat the inhibited areas for wiring equivalently with respect to the connection pins, and imaginarily dividing the chip into lattices and subsequently uniforming a ratio of a sum of the numbers of the connection pins and the equivalent pins to a region capable of arrangement in each lattice, whereby a position of each logic cell is determined.

Claims

1. An arrangement method for logic cells in a semiconductor IC device, in which a plurality of logic cells are arranged on a semiconductor chip and wiring is performed between the logic cells so as to realize a desired circuit, comprising the steps of:

(a) expressing the logic cell informations to be arranged on the chip and already-arranged cell and wiring informations by means of connection pins and inhibited areas for wiring, respectively;

(b) expressing the inhibited areas for wiring as the equivalent number of the connection pins so as to equivalently treat the inhibited areas for wiring as the connection pins;

(c) imaginarily dividing the chip into lattices;

(d) evaluating a distribution of a sum of the number of the connection pins and the equivalent number of the connection pins within each lattice, based on a ratio of the sum of the number of the connection pins and the equivalent number of the connection pins to an area capable of arrangement in such lattice;

(e) extracting a desired lattice, if the ratio in at least one of said lattices falls outside a permitted value; and

(f) exchanging the logic cells among the lattices; and

(g) updating the distribution within said each lattice and repeating steps (e) to (f) until the ratio in said each lattice falls within the permitted value.

2. An arrangement method for logic cells in a semiconductor IC device, in which a plurality of logic cells are arranged on a semiconductor chip and wiring is performed between the logic cells so as to realize a desired circuit, comprising the steps of:

(a) expressing cell informations to be arranged on a chip and already-arranged cell and wiring informations by means of connection pins and inhibited areas for wiring, respectively;

(b) performing conversion processing to equivalently treat the inhibited areas for wiring and the connection pins, and expressing the inhibited areas for wiring as the equivalent number of the connection pins;

(c) imaginarily dividing the chip into lattices;

(d) designating a plurality of box regions each including a first predetermined number of lattices;

(e) evaluating a distribution of a sum of the number of the connection pins and the equivalent number of the connection pins within each box region, based on a ratio of the sum of the number of the connection pins and the equivalent number of the connection pins to an area capable of arrangement in each lattice within each box region;

(f) selecting a predetermined box region from said plurality of box regions;

(g) extracting a desired lattice, if the ratio in at least one of said lattices falls outside a first permitted value within said predetermined box region;

(h) exchanging the logic cells among the lattices within said predetermined box region;

(i) updating the distribution within said each lattice and repeating steps (g) to (h) until the ratio in said each lattice falls within the first permitted value within said predetermined box region;

(j) selecting another predetermined box region and repeating the steps (g) to (i) until the ratio falls within the first permitted value;

(k) setting a plurality of another box regions each including a second predetermined number of lattices; and

(l) repeating steps (e) to (j) until the ratio in said each lattice falls within a second permitted value within said predetermined box region.

3. An arrangement method for logic cells according to claim 2, wherein said plurality of another box regions in step (k) have a size different from that of said plurality of box regions in step (d).

4. An arrangement method for logic cells in a semiconductor IC device, in which an arrangement of a plurality of logic cells on a semiconductor chip and wiring between the logic cells is determined so as to realize a desired circuit, comprising the steps of:

(a) expressing cell informations to be arranged on the chip and already-arranged cell and wiring informations by means of connection pins and inhibited areas for wiring, respectively;

(b) performing conversion processing to equivalently treat the inhibited areas for wiring and the connection pins, and expressing the inhibited areas for wiring as the equivalent numbers of the connection pins;

(c) imaginarily dividing the chip into lattices;

(d) designating a plurality of box regions each including a predetermined number of lattices;

(e) evaluating a distribution of a sum of the number of the connection pins and the equivalent number of the connection pins within each box region, based on a ratio of the sum of the number of the connection pins and the equivalent number of the connection pins to an area capable of arrangement in each lattice within each box region;

(f) selecting a predetermined box region from said plurality of box regions;

(g) extracting the lattice having the maximum equivalent number of the connection pins, it the ratio falls outside a first permitted value within said predetermined box region;

(h) calculating a moving direction of the logic cell in which the number of wirings extending across cutlines of a lattice including the cell is minimized and moving the cell to an adjacent lattice which is located in the calculated direction;

(i) updating the distribution and repeating steps (g) to (h) until the ratio of the sum of number of the connection pins and the equivalent number of the connection pins to the area capable of arrangement in each lattice falls within the first permitted value within said predetermined box region; and

(j) selecting another box region and repeating the steps (g) to (i) until the ratio falls within a second permitted value.