dRAM cell and method

• US 5,225,697 A
• Filed: 03/26/1992
• Issued: 07/06/1993
• Est. Priority Date: 09/27/1984
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Pollack, Gordon P., Richardson, William F., Malhi, Satwinder S.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Crane, Sara W.
• Application Number:
  US07/859,286
• Time in Patent Office: 467 Days
• Field of Search: 357/23.6, 357/236 G, 357/23.4, 357/51, 357/55, 357/71, 357/715, 357/71 P
• US Class Current: 257/302
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel and drain and one capacitor plate are formed essentially vertically in the bulk substrate sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench and isolated from the bulk by an insulating layer. Signal charge is stored on the capacitor material inserted into the trench by an electrical connection of the bulk substrate source to the capacitor material through the insulating layer. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface form the drains. The trenches and cells are formed at the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.

Claims

1. A memory cell comprising:

a substrate having a trench formed therein;

a capacitor having a first capacitor plate formed substantially in a first portion of said trench, said first portion of said trench being disposed away from the mouth of said trench relative to a second portion of said trench, and said substrate serving as a second capacitor plate, said first and second capacitor plates separated by an insulating material; and

a transistor comprising;

a source region formed in said substrate and encircling said trench in a plane substantially perpendicular to the major axis of said trench and directly connected to said first capacitor plate, a drain region formed in said substrate and encircling said trench in a plane substantially perpendicular to the major axis of said trench and a gate formed in said second portion of said trench.

2. A memory cell as in claim 1 wherein said first capacitor plate comprises polycrystalline silicon.

3. A memory cell as in claim 1 wherein said first capacitor plate is in physical contact with said source region.

7. A memory cell as in claim 2 including a conductor connected to said first capacitor plate and said source region and passing through said insulating layer.

4. A memory array comprising:

a substrate having a plurality of trenches formed therein;

a plurality of memory cells, each memory cell comprising;

a capacitor having a first capacitor plate formed substantially in a first portion of one of said trenches, said first portion of said trench being disposed away from the mouth of said trench relative to a second portion of said trench, and said substrate serving as a second capacitor plate, said first and second capacitor plates separated by an insulating material; and

a transistor comprising;

a source region formed in said substrate and encircling said trench in a plane substantially perpendicular to the major axis of said trench and directly connected to said first capacitor plate, a drain region formed in said substrate and encircling said trench in a plane substantially perpendicular to the major axis of said trench and a gate formed in said second portion of said trench.

5. A memory array as in claim 4 wherein said first capacitor plate comprises polycrystalline silicon.

6. A memory array as in claim 4 wherein said first capacitor plate is in physical contact with said source region.

8. A memory cell as in claim 5 including a conductor connected to said first capacitor plate and said source region and passing through said insulating layer.

9. A device comprising:

(a) a substrate with a trench formed therein;

(b) a capacitor plate within said trench substantially insulated from said substrate; and

(c) a field effect transistor having a channel positioned to provide current substantially along the walls of said trench to said plate.

10. Device as in claim 9 wherein said channel surrounds the upper portion of said trench.

11. Device as in claim 9 wherein said channel is disposed in said substrate.

12. Device as in claim 9 wherein a substantial region of said substrate surrounding the isolated portion of said capacitor is a type from the group of N+ and P-.

13. A device comprising:

(a) a layer of semiconductor material of first conductivity type having at least a wall;

(b) a conductor spaced from said wall by an insulator;

(c) a doped region of a second conductivity type between said insulator and said layer of semiconductor material; and

(d) a conductive material connecting said conductor to said doped region, a first portion of said wall is the channel of a transistor and said conductor is one plate of a capacitor and a second portion of said wall opposite said conductor is another plate of said capacitor.

14. Device as in claim 13 wherein said wall forms a part of a trench.

15. Device as in claim 13 wherein said conductive material is in contact with said conductor.

16. Device as in claim 13 wherein said layer of semiconductor material includes a substrate and a layer of epitaxial material and said wall extends through at least part of said layer of epitaxial material.

17. Device as in claim 13 wherein said conductor is one plate of a capacitor.

18. Device as in claim 13 wherein said conductive material is between said wall and said conductor.

19. A device comprising:

(a) a layer of semiconductor material of a first conductivity type having at least first and second surfaces and a wall, said wall extending between and at an angel to said first and second surfaces, said first surface being spaced from said second surface;

(b) a conductor spaced from said wall by an insulator;

(c) a doped region of a second conductivity type between said insulator and said layer of semiconductor material; and

(d) a conductive material connecting said conductor to said doped region, a first portion of said wall is the channel of a transistor and said conductor is one plate of a capacitor and a second portion of said wall opposite said conductor is another plate of said capacitor.