Making and testing an integrated circuit using high density probe points

• US 5,225,771 A
• Filed: 10/11/1991
• Issued: 07/06/1993
• Est. Priority Date: 05/16/1988
• Status: Expired due to Fees

• Current Assignee: ELM TECHNOLOGY CORPORATION
• Original Assignee: DRI Technology Corporation
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Karlsen, Ernest F.
• Assistant Examiner(s): BURNS, WILLIAM
• Application Number:
  US07/775,324
• Time in Patent Office: 634 Days
• Field of Search: 324/725, 324/158 P, 324/158 F, 439/66, 439/80, 439/86, 439/89-91, 156/647
• US Class Current: 324/755.04
• CPC Class Codes: G01R 1/06716 Elastic
• CPC Class Codes: G01R 1/06761 related to layers
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/316 Testing of analog circuits G01R31/2851 takes precedence
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31912 Tester/user interface
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure.

Claims

1. A tester surface comprising:

a substrate formed of a flexible material;

a plurality of probe points extending from the substrate, each probe point including an outer layer of the same flexible material forming a continuous layer with the flexible material of the substrate and an inner layer of conductive metal formed within the outer layer defining an enclosed respective cavity, wherein the probe point is resiliently compressible.

2. A test surface comprising:

a substrate formed of a flexible material;

a plurality of probe points extending from the substrate, each probe point including an outer layer of flexible material defining an enclosed respective cavity and having an inner layer of conductive metal formed within the outer layer, wherein the outer layer is of the same material as and forms a single continuous layer with the substrate, wherein the probe point is resiliently compressible by at least 10% of its length.

3. The device of claim 2, wherein the cavity of each probe point is filled with a fluid.

4. The device of claim 2, wherein the cavity of each probe point is filled with an elastomeric polymer.

5. The device of claim 2, wherein each probe point includes a metal tip formed on an end of the probe point farthest from the substrate, the tip being in electrical contact with the inner layer.

6. The device of claim 2, wherein the substrate comprises a polymer film less than 10 μ

m in thickness.

7. The device of claim 2, wherein the tester surface includes at least 1000 probe points.

8. The device of claim 2, wherein each probe point has a maximum outside diameter of less than one mil.

9. The device of claim 2, further comprising a rigid substrate layer on which said first layer of flexible material is formed.

11. The device of claim 2, wherein each probe point has a diameter of about four micrometers or less.

12. The device of claim 2, wherein a sidewall of each probe point including the outer layer of conductive material and the inner layer of conductive material has a thickness of less than about 4000 Å

.

13. The device of claim 5, wherein the metal tip is located at the extremity of an elongated extension of the inner layer of conductive metal extending outwards from said cavity.

14. The device of claim 13, wherein the elongated extension is capable of bending at least 10% of its length.

15. The device of claim 2, wherein adjacent probe points have a spacing center-to-center of less than about six micrometers.

16. The device of claim 2, wherein said flexible material comprises low stress silicon nitride.

17. The device of claim 16, wherein each probe point includes a conductive tip formed on an end of the probe point farthest from the substrate, the tip being in electrical contact with the inner layer.

10. A tester surface comprising:

a substrate formed of a flexible material;

a plurality of probe points extending from the substrate, each probe point including an outer layer of flexible material defining a respective cavity and having an inner layer of conductive metal formed within the outer layer, wherein the outer layer is joined to the substrate, wherein the probe point is resiliently compressible by at least 10% of its length, and

wherein both the substrate and the outer layer comprise low stress silicon dioxide.