Automatic test equipment system using pin slice architecture

• US 5,225,772 A
• Filed: 09/05/1990
• Issued: 07/06/1993
• Est. Priority Date: 09/05/1990
• Status: Expired due to Term

• Current Assignee: Xcerra Corporation (COHU Incorporated)
• Original Assignee: Schlumberger Technologies Incorporated (SLB)
• Inventors: Graeve, Egbert, Cheung, David K.
• Primary Examiner(s): NGUYEN, VINH P
• Application Number:
  US07/577,987
• Time in Patent Office: 1,035 Days
• Field of Search: 324/158 R, 324/73.1, 371/15.1, 371/25.1, 371/27
• US Class Current: 324/73.1
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G01R 31/31921 using compression techniques, e.g. patterns sequencer
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

A plurality of "pin slice" circuits, each associated with a separate pin of the device under test (DUT). Each pin slice circuit contains its own memory and registers and circuitry for generating the necessary test signals. Test data is loaded into the individual pin slice circuits in a vertical word fashion, such that all of the bits of the vertical word correspond to the individual pin, allowing the characteristics of an individual pin test sequence to be varied independently of the other pins. A participate memory is used to select different groupings of the pin slice circuits which are to be programmed in parallel when a group of pins are to receive the same test signals. Separate enable signals to the various stages of the pin slice circuits allow different aspects of the test pattern to be also varied independently.

Claims

1. A tester for multiple pin integrated circuits, comprising:

(a) a plurality of pin slice circuits, each coupled to a separate pin connector, each pin slice circuit including,

(1) a local memory having a single bit I/O and a plurality of addresses, for storing a string of data to be applied to said pin connector,

(2) event sequencing means, coupled to an output of said local memory, for providing timing control of said data and including a sequencer memory for storing a plurality of timing criteria,

(3) driver means, coupled between said event sequencing means an said pin connector, for driving signals to said pin connector,

(4) levels generator means, coupled to said driver means, for providing appropriate voltage and current level so said driver means and including a voltage memory for storing voltage and current levels, and

(5) a participate memory for storing an indication that said pin slice circuit belongs to a combination of said pin slice circuits to be programmed with identical data, having an output coupled to an enabling input of said pin closed circuit;

such that separate patterns can be written into said local memories, sequencer memories and voltage memories for independent grouping of said pin slice circuits.

2. The tester of claim 1 wherein each said pin slice circuit further includes a scrambler memory having data outputs coupled to address inputs of said sequencer memory, said scrambler memory being programmable so that a single address provided to the scrambler memory for all pin slice circuits can select different addresses in said sequencer memories for different pin slice circuits.

3. The tester of claim 1 wherein each said pin slice circuit further includes means for buffering a data stream coupled to an output of said local memory.

4. The tester of claim 3 wherein said means for buffering a data stream comprises a first-in, fist-out register.

5. The tester of claim 1 wherein each said pin slice circuit further includes

a comparator, coupled to said pin connector, for evaluating an output of said integrated circuit;

a capture memory, coupled to said comparator for storing a pass or fail indication for a plurality of tests; and

a cumulative fail memory location in said capture memory, for storing a fail signal if any location in said capture memory has a fail signal written to it;

such that said capture memory will contain all pass signals, and thus need not be read, unless said cumulative fail memory location contains a fail signal.

6. A tester for multiple pin integrated circuits, comprising:

a plurality of pin slice circuits, each coupled to a separate pin connector, each pin slice circuit including,

(1) a local memory having a single bit I/O and a plurality of addresses, for storing a string of data to be applied to said pin connector,

(2) event sequencing means, coupled to an output of said local memory, for providing timing control of said data and including a sequencer memory for storing a plurality of timing criteria,

(3) driver means, coupled between said event sequencing means and said pin connector, for driving signals to said pin connector,

(4) levels generator means, coupled to said driver means, for providing appropriate voltage and current levels to said driver means and including a voltage memory for storing voltage and current levels,

(5) a first participate memory for storing data at addresses which indicate if said local memory is to be used for a grouping of pin slice circuits indicated by said addresses having an output coupled to an enabling input of said local memory,

(6) a second participate memory for storing data at addresses which indicate if said voltage memory is to be used for a grouping of pin slice circuits indicated by said addresses having an output coupled to an enabling input of said voltage memory, and

(7) a scrambler memory having data outputs coupled to address inputs of said sequencer memory, said scrambler memory being programmable so that a signal address provided to the scrambler memory for all pin slice circuits can select different addresses in said sequencer memories for different pin slice circuits;

such that separate patterns can be written into said local memories, sequencer memories and voltage memories for independent grouping of said pin slice circuits.

7. The tester of claim 6 wherein each said pin slice circuit further includes a first-in, first-out register coupled to an output of said local memory.

8. The tester of claim 6 wherein each said pin slice circuit further includes

a comparator, coupled to said pin connector, for evaluating an output of said integrated circuit;

a capture memory, coupled to said comparator for storing a pass or fail indication for a plurality of tests; and

a cumulative fail memory location in said capture memory, for storing a fail signal if any location in said capture memory has a fail signal written to it;

such that said capture memory will contain all pass signals, and thus need not be read, unless said cumulative fail memory location contains a fail signal.