Field sequential liquid crystal display with memory integrated within the liquid crystal panel

• US 5,225,823 A
• Filed: 12/04/1990
• Issued: 07/06/1993
• Est. Priority Date: 12/04/1990
• Status: Expired due to Term

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Kanaly, David B.
• Primary Examiner(s): Chin, Tommy P.
• Assistant Examiner(s): Chin, Jick
• Application Number:
  US07/621,961
• Time in Patent Office: 945 Days
• Field of Search: 340/767, 340/784, 340/793, 340/800, 340/762, 340/782, 340/750, 340/780, 340/811, 340/718, 340/719, 350/332, 350/333, 359/54, 359/55, 359/56
• US Class Current: 345/89
• CPC Class Codes: G09G 2300/0828 forming a digital to analog [D/A] conversion circuit
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/3406 Control of illumination source illumination devices structurally associated with liquid crystal cells G02F1/1336
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3651 using multistable liquid crystals, e.g. ferroelectric liquid crystals

Abstract

A field sequential liquid crystal display has a backlight that provides different color fields and a liquid crystal display panel that has a matrix of cells. Data lines are coupled to the cells and provide gray level data to the cells. Select lines are coupled to the cells and enable the cells. The cells include integrated memories coupled to the data lines, these integrated memories storing gray level data received via the data lines. The integration of the memories on the display panel allows all of the cells on the panel to be charged approximately simultaneously so that the time any one color is backlighting the entire display approaches an optimum fraction of a frame.

Claims

1. A liquid crystal display panel made of ferroelectric liquid crystal, comprising:

a matrix of cells;

data lines coupled to the cells and which provide gray level data to the cells;

select lines coupled to the cells and which enable the cells;

wherein each cell includes a plurality of shift registers coupled to the data lines, with each shift register storing gray level data received via said data lines for a plurality of fields within a frame;

wherein each cell includes a main cell capacitance and means for controlling a duration of time that the main cell capacitance is transmissive, said duration of time being proportional to said gray level data stored in one of said shift registers, wherein the means for controlling a duration of time includes;

a switch coupled to the main cell capacitance that in a first position causes said main cell capacitance to be transmissive and in a second position causes said main cell capacitance to be maximally opaque, a momentary switch closure circuit coupled between the plurality of shift registers and the switch, said momentary switch closure circuit controlling the switch; and

a counter coupled to the momentary switch closure circuit and controlling said momentary switch closure circuit.

2. The panel of claim 1, wherein each cell has two said shift registers, each said shift register being a twenty-four bit shift register, each said frame having three fields, and further comprising means for switching the two shift registers such that one shift register is storing gray level data for one frame while the other shift register is providing gray level data to the main cell capacitance for a previous frame.