Communication interface between a radio control transmitter and a computer data bus

• US 5,226,124 A
• Filed: 06/05/1991
• Issued: 07/06/1993
• Est. Priority Date: 06/05/1991
• Status: Expired due to Fees

• Current Assignee: Ambrosia Microcomputer Products Incorporated
• Original Assignee: Ambrosia Microcomputer Products Incorporated
• Inventors: Stern, David R.
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): Ray, Gopal C.
• Application Number:
  US07/710,469
• Time in Patent Office: 762 Days
• Field of Search: 364/DIG. 1 MS File, 364/DIG. 2 MS File, 364/480, 364/486, 364/487, 364/488, 395/325, 395/250, 395/275, 395/775, 395/375, 395/100, 341/176, 340/825.69, 340/825.72, 455/91, 370/85.1, 370/110.1, 342/195, 446/454, 273/438, 358/194.1
• US Class Current: 710/72
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence
• CPC Class Codes: G06F 3/038 Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry

Abstract

An interface circuit for use between a radio control transmitter equipped with joysticks and a standard data bus of a personal type computer. The interface circuitry includes a microcontroller operated as a reformatter for signals received from the remote control transmitter and a number of integrated circuit latch and buffer circuits connected between the output of the microcontroller and the data bus of a computer to convert the signals output from the microcontroller to the data bus on a direct basis.

Claims

1. An interface circuit for use between a radio control transmitter equipped with encoded signal outputs and a computer data bus, said interface circuit comprising:

a microprocessor including incoming circuit connections from said radio control transmitter encoded signal outputs;

a first latch including incoming circuit connections from said microprocessor;

a second latch including outgoing circuits to said microprocessor;

a bidirectional buffer including incoming circuit connections from said first latch and including outgoing circuit connections to said second latch, said bi-directional buffer further including bidirectional circuit connections to said computer data bus; and

a first one-way buffer including incoming circuit connections from said computer data bus and an outgoing circuit connection to said bidirectional buffer, said first one-way buffer operated in response to signals received from said computer via said data bus to control the direction of flow of information through said bidirectional buffer from said first latch to said computer data bus or in the alternative from said computer bus to said second latch.

2. An interface circuit as claimed in claim 1 wherein:

there is further included a second one-way buffer including circuit connections from said computer data bus; and

a logic circuit including incoming circuit connections from said first and second one-way buffers and including outgoing circuit connections to said bidirectional buffer, operated in response to incoming signals from said computer data bus to enable the transmission of information through said bidirectional buffer.

3. An interface circuit as claimed in claim 1 wherein:

there is further included a one-way outgoing buffer including an incoming circuit connection from said microprocessor and an outgoing circuit connection to said computer data bus, said one-way outgoing buffer operated to transfer interrupt signals from said microprocessor to said computer data bus, said interrupt signal indicative of an indication by said microprocessor as ready to transmit information to said computer.

4. An interface circuit as claimed in claim 2 wherein:

said logic circuit further includes a comparator circuit comparing signals received over incoming circuit connections from said one-way buffers and from an eight bit address source; and

said logic circuit operated in response to an output signal from said comparator circuit and said incoming signals from said computer bus to control transmission of information through said bidirectional buffer.

5. An interface circuit as claimed in claim 1 wherein:

said second latch further includes an incoming circuit connection from said microprocessor.

6. An interface circuit as claimed in claim 1 wherein:

said outgoing circuit connection from said first one-way buffer further connects to said first latch to extend signals to control the output of said latch.

7. An interface circuit as claimed in claim 1 wherein:

operating power for said interface circuit is derived from said computer bus.

8. An interface circuit as claimed in claim 3 wherein:

said interface circuit is operated in response to an interrupt circuit from said microprocessor transmitted via said one-way outgoing buffer to said computer data bus to control the direction of information coupled through said bidirectional buffer bus in response to signals received back from said computer bus to said first incoming buffer circuit.

9. An interface circuit as claimed in claim 1 wherein:

said radio control transmitter includes a trainer output connected to said microprocessor'"'"'s timer input to determine the value of data transmitted from said radio control transmitter to said interface circuit.

10. An interface circuit as claimed in claim 1 wherein:

said radio control transmitter transmits data to said interface circuit in a coded bit stream employing pulse position modulation, or in the alternative employing pulse code modulations.

11. An interface circuit as claimed in claim 1 wherein:

said interface circuit is included in said radio control transmitter.