Switch matrix having integrated crosspoint logic and method of operation

• US 5,226,125 A
• Filed: 11/17/1989
• Issued: 07/06/1993
• Est. Priority Date: 11/17/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Guttag, Karl M., Balmer, Keith, Gove, Robert J., Ing-Simmons, Nicholas K.
• Primary Examiner(s): RICHARDSON, ROBERT
• Application Number:
  US07/437,875
• Time in Patent Office: 1,327 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2, 340/825.79, 340/825.5, 340/825.51, 370/62, 370/58.3, 370/58.1, 395/200, 395/325
• US Class Current: 710/317
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer

Abstract

There is disclosed a switch matrix and operational method relying upon a high degree of operational logic at each matrix crosspoint. In one embodiment, the switch is used in a multiprocessor system arranged as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. The switch matrix serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories and is contained on a single silicon substrate.

Claims

1. A switch matrix for interconnecting a plurality of first ports with a plurality of second ports, said switch matrix comprising:

a plurality of vertical buses, each said bus associated with a particular one of said first ports;

a plurality of individually operable crosspoints;

a plurality of horizontal buses connected to said second ports for connecting, via enabled ones of said crosspoints, one of said first ports and any one of said second ports; and

contention handling circuitry, disposed at each crosspoint, associated with each vertical bus for handling contention between competing ones of said second ports for connection to said vertical bus.

2. The switch matrix as set forth in claim 1 wherein said contention handling circuitry at each crosspoint of a particular vertical bus includes circuitry for receiving a permanent address designation of said first port associated with said vertical bus, and wherein:

said contention handling circuitry at each crosspoint of a particular horizontal bus includes circuitry for receiving from time to time first port address designations of desired connections through said matrix from said second port associated with said horizontal bus to a particular first port.

3. The switch matrix as set forth in claim 1 wherein said contention handling circuitry at each said crosspoint includes token passing logic for granting one of said crosspoints associated with each said vertical bus first priority in the event of receipt of the same second port address designation from more than one of said second ports.

4. The switch matrix as set forth in claim 1 wherein said crosspoints, as well as said contention handling circuitry, are distributed spatially on said single chip in conjunction with said first and second ports.

5. The switch matrix as set forth in claim 1, further comprising:

a plurality of memories, each memory connected to a corresponding one of said first ports; and

a plurality of data processors, each data processor connected to a corresponding one of said second ports.

6. The switch matrix as set forth in claim 5 wherein said switch matrix is constructed on different layers of a single chip.

7. A switch matrix for interconnecting a plurality of first ports with a plurality of second ports, said switch matrix constructed on a single substrate and comprising:

a plurality of buses in one level of said substrate, each said bus associated with a particular one of said first ports;

a plurality of individually operable crosspoints;

a plurality of horizontal buses in another level of said substrate connected to said second ports for connecting, via enabled ones of said crosspoints, one of said first ports and any one of said second ports; and

contention handling circuitry disposed at each crosspoint with each vertical bus for handling contention between competing ones of said second ports for connection to said vertical bus.

8. The switch matrix as set forth in claim 7 wherein said contention handling circuitry at each crosspoint of a particular vertical bus includes circuitry for receiving a permanent address designation of said first port associated with said vertical bus, and wherein:

said contention handling circuitry at each crosspoint of a particular horizontal bus includes circuitry for receiving from time to time first port address designations of desired connections through said matrix from said second port associated with said horizontal bus to a particular first port.

9. The switch matrix as set forth in claim 7 wherein said contention handling circuitry at each said crosspoint includes token passing logic for granting one of said crosspoints associated with each said vertical bus first priority in the event of receipt of the same second port address designation from more than one of said second ports.

10. The switch matrix as set forth in claim 7 wherein said crosspoints, as well as said contention handling circuitry, are distributed spatially on said substrate in conjunction with said first and second ports.

11. The method set forth in claim 7 further comprising the steps of:

allowing separate processors to have access to any of said memories over said switch matrix, and wherein said prioritization system further includes the step of giving lowest priority to said separate processor for each said memory.

12. The method of operating a switch matrix in a processing system where the processing system has a plurality of first ports connectable to any one of a plurality of second ports and where said switch matrix has a first set of links connected to said first ports and a second set of links connected to said second ports, said sets of links spatially separated from each other and connectable together by a plurality of selectively operable crosspoints, said method comprising the steps of:

sending to said crosspoints from an active one of said first ports via said first set of links an address designating a desired connection through said switch matrix to a particular one of said second ports;

receiving at each of said crosspoints all of said sent addresses;

resolving at said crosspoints any contention between said first ports sending addresses designating the same second port; and

enabling one of said crosspoints, by circuitry at said crosspoint, in response to said resolved contention so as to effect a connection from said active first port to said second port corresponding to said address designating a desired connection through said switch matrix.

13. The method set forth in claim 12 wherein said crosspoint contention handling circuitry is operative to provide contention by a token passing arrangement.

14. The method set forth in claim 12 wherein each said crosspoint includes a prioritization control system and wherein said method further includes the step of:

granting only one of a set of simultaneous processor access attempts to the same memory.

15. The method set forth in claim 14 wherein said prioritization system includes the step of sequential token passing.

16. The method set forth in claim 15 wherein said first ports are processors having data ports and wherein said second ports are memories and wherein said token passing step includes the step of:

insuring lowest priority memory access to the processor which last successfully accessed the memory associated with said crosspoint.

17. The method set forth in claim 16 further comprising the step of:

allowing separate processors to have access to any of said memories over said switch matrix, and wherein said prioritization system further includes the step of giving lowest priority to said separate processor for each said memory.

18. The method set forth in claim 12, wherein a subset of said first ports are connected to a single first link, further comprising the steps of:

selectively splitting said single first link whereby when not split said subset of said first ports may be connected in common to a predetermined one of said second ports via said crosspoints and when split each first port of said subset of first ports may be independently connected to corresponding different second ports via said crosspoints.

19. The method set forth in claim 18 wherein each first port is a processor having at least two data ports and wherein said second ports are memories, and wherein said method further includes the steps of:

connecting one of said data ports through said switch matrix to all of said memories; and

connecting the other of said data ports through said split links of said switch matrix to a specific subset of said memories.

20. The method set forth in claim 19 wherein said processors each have at least one instruction port and wherein said method further includes the step of:

connecting said instruction port of each said processors via a specific dedicated instruction link of said switch matrix to a specific memory.

21. The method set forth in claim 20 further including the steps of:

inhibiting a connection from each said dedicated instruction link to said specific memory; and

concurrently enabling a common connection from said instruction port of all said processors to one common memory.

22. The method set forth in claim 21 further including the step of:

connecting together said split links on a cycle-by-cycle basis.

23. The method set forth in claim 12, wherein:

said step of resolving of said crosspoints any contention includes maintaining at each of said crosspoints of a particular second link a particular one of said first ports to have priority in the event of said contention.

24. The method set forth in claim 12, wherein

said step of resolving of said crosspoints any contention includes setting at each of said crosspoints of a particular second link a lowest priority to a first port most recently connected to said particular second link.