Memory cartridge bank selecting apparatus

• US 5,226,136 A
• Filed: 11/05/1990
• Issued: 07/06/1993
• Est. Priority Date: 05/06/1986
• Status: Expired due to Term

• Current Assignee: Nintendo Company Limited
• Original Assignee: Nintendo Company Limited
• Inventors: Nakagawa, Katsuya
• Primary Examiner(s): Kulik, Paul V.
• Application Number:
  US07/610,198
• Time in Patent Office: 974 Days
• Field of Search: 364/200, 364/900, 364/410, 395/425, 395/164, 395/166, 395/400, 365/230.03, 273/85 G
• US Class Current: 463/44
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory cartridge is loaded in a main unit of a personal computer when used. The memory cartridge comprises a case, and a printed circuit board which is installed therein and on which a large-capacity, one-chip ROM is mounted. Storage area of the one-chip ROM is divided into a plurality of banks respectively having memory addresses of a number accessible by a central processing unit of the main unit, and one specific bank among them is allocated to an address space accessible all the time by the central processing unit. Bank selecting data for selecting other banks is stored in that specific bank. The bank selecting data is read out with progress of a program stored in the specific bank, being loaded in a counter. The content of the counter is inputted to the most significant three bits of address of the one-chip ROM. The most significant three bits of the address function as bank designating bits. An arbitrary bank of the one-chip ROM is changed over at an arbitrary timing by the bank selecting data outputted from the other banks of the one-chip ROM.

Claims

1. External memory apparatus which is removably connectable to a video game apparatus having a microprocessor (MPU), a picture processing unit (PPU) coupled to said MPU, and an edge connector, said MPU being connected to a MPU data bus and a MPU address bus and said PPU being connected to a PPU address bus and a PPU data bus, said MPU data bus, MPU address bus, PPU data bus and PPU address bus being connected to said edge connector, said external memory apparatus comprising:

an array of connecting electrodes connected to said edge connector when said external memory apparatus is loaded into said video game apparatus, said array of connecting electrodes including a first plurality of electrodes disposed to receive in use signal from said MPU address bus, said MPU data bus, said PPU address bus, and said PPU data bus, and a second plurality of electrodes disposed to receive in use memory accessing related signals generated by said microprocessor;

memory means for storing video game related information, said memory means having memory address terminals, at least a predetermined portion of said memory address terminals being coupled to at least some of said first plurality of connecting electrodes, said memory means having memory data terminals coupled to at least some of first plurality of connecting electrodes;

said memory means including a plurality of memory banks; and

a data holding circuit for storing bank selecting data, said data holding circuit having at least one input terminal coupled to at least some of said first plurality of electrodes and having at least one output terminal, said at least one output terminal being connected to at least one of said memory address terminals to provide bank specifying data to said memory means;

said data holding circuit being coupled to at least some of said second plurality of electrodes, wherein said data holding circuit is loaded with bank selecting data received via said at least one input terminal in response to at least one memory accessing related signal received via said second plurality of electrodes.

2. External memory apparatus according to claim 1, wherein said data holding circuit has a clock input, said clock input being connected to a predetermined one of said second plurality of electrodes.

3. External memory apparatus according to claim 2, wherein said memory means includes a program memory and a character memory, and wherein said memory means has a chip-enable input which is coupled to said predetermined one of said second plurality of electrodes.

4. External memory apparatus according to claim 1, wherein said data holding circuit has a load input, said load input being coupled to receive a read/write signal from one of said second plurality of electrodes.

5. External memory apparatus according to claim 1, wherein said data circuit provides, via said at least one output terminal, the most significant bits of a memory address to said memory address terminals of said memory means.

6. External memory apparatus which is removably connectable to a video game apparatus having a microprocessor (MPU), a picture processing unit (PPU) coupled to said MPU, and an edge connector, said MPU being connected to a MPU data bus and a MPU address bus and said PPU being connected to a PPU address bus and a PPU data bus, said MPU data bus, MPU address bus, PPU data bus and PPU address bus being connected to said edge connector, said external memory apparatus comprising:

an array of connecting electrodes connected to said edge connector when said external memory apparatus is loaded into said video game apparatus, said array of connecting electrodes including a first plurality of electrodes disposed to receive in use signals from said MPU address bus, said MPU data bus, said PPU address bus, and said PPU data bus, and a second plurality of electrodes disposed to receive in use memory accessing related signals generated by said microprocessor;

memory means for storing at least one video game program and for storing character data related to said video game program, said memory means having address terminals, a first predetermined portion of said address terminals being coupled to at least some of said first plurality of connecting electrodes, and having data terminals coupled to at least some of first plurality of connecting electrodes, said memory means including a plurality of memory banks;

a data holding circuit for storing bank selecting data, said data holding circuit having at least one input terminal coupled to at least some of said first plurality of electrodes and having at least one output terminal connected to at least one of said address terminals;

said data holding circuit being coupled to at least one of said second plurality of electrodes, wherein said data holding circuit has at least one load controlling input for controlling loading of bank selecting data received via said at least one input terminal, said load controlling input being coupled to receive a read/write signal via said second plurality of electrodes.

7. External memory apparatus according to claim 6, wherein said at least one load controlling input further includes a clock input, said clock input being connected to a predetermined one of said second plurality of electrodes.

8. External memory apparatus according to claim 7, wherein said memory means has a chip enable input which is coupled to said predetermined one of said second plurality of electrodes.

9. External memory apparatus according to claim 6, wherein said memory means includes a program memory and a character memory.

10. External memory apparatus according to claim 9, wherein said data holding circuit provides, via said at least one output, the most significant bits of a memory address to said program memory.

11. Removable apparatus which is removably connectable to a video game apparatus having a microprocessor (CPU), a picture processing unit (PPU) coupled to said microprocessor, and an edge connector, said microprocessor being connected to a CPU data bus and a CPU address bus and said picture processing unit being connected to a PPU address bus and a PPU data bus, said CPU data bus, CPU address bus, PPU address bus and PPU data bus being connected to said edge connector, said removable apparatus comprising:

an array of connecting electrodes connected to said edge connector when said removable apparatus is loaded into said video game apparatus, said array of connecting electrodes including a first plurality of electrodes disposed to receive in use signals from said CPU address bus, a second plurality of electrodes being disposed to receive in use signals from said CPU data bus, a third plurality of electrodes disposed to receive in use signals from said PPU address bus, a fourth plurality of electrodes disposed to receive in use signals from said PPU data bus, and a fifth plurality of electrodes disposed to receive in use memory accessing related signals generated by said microprocessor;

a plurality of memory blanks, addressable via a plurality of address terminals at least one of said memory banks being coupled to at least some of said connecting electrodes;

a control circuit connected to at least one of said fifth plurality of electrodes, and to at least one of said second plurality of electrodes, said control circuit being responsive to at least one of said memory access related signals generated by said microprocessor and including a data holding circuit for generating at least one memory bank access enabling signal for for coupling to at least one of said plurality of address terminals for selecting one of said plurality of memory banks based at least in part on the contents of said data holding circuit, said data holding circuit having at least one data load controlling input coupled to receive in CPU generated read/write signal for temporarily storing memory bank selecting data received via said at least one of said second plurality of electrodes.

12. External memory apparatus according to claim 11, wherein at least one of said memory banks has a chip enable input which is coupled to receive at least one of the memory access related signals.

13. External memory apparatus according to claim 11, wherein said plurality of memory banks are embodied in the same memory device.

14. External memory apparatus according to claim 11, wherein the state of at least one bit stored in said data holding circuit determines which of said plurality of memory banks will be accessed.

15. External memory apparatus which is removably connectable to a video game apparatus having a microprocessor (MPU), a picture processing unit (PPU) coupled to said MPU, and an edge connector, said MPU being connected to a MPU data bus and a MPU address bus and said PPU being connected to a PPU address bus and a PPU data bus, said MPU data bus, MPU address bus, PPU data bus and PPU address bus being connected to said edge connector, said external memory apparatus comprising:

an array of connecting electrodes connected to said edge connector when said external memory apparatus is loaded into said video game apparatus, said array of connecting electrodes including a first plurality of electrodes disposed to receive in use signals from said MPU address bus, and said MPU data bus, a second plurality of electrodes disposed to receive in use signals from said PPU address bus, and said PPU data bus, and a third plurality of electrodes disposed to receive in use memory accessing related signals generated by said microprocessor;

a first digital memory for storing at least one video game program, said first digital memory having address terminals, a first predetermined portion of said address terminals being coupled to at least some of said first plurality of connecting electrodes, said first digital memory having data terminals coupled to at least some of first plurality of said connecting electrodes, said first digital memory being divided into a plurality of memory banks;

a second digital memory for storing character data related to said video game program, said second digital memory being coupled to at least some of said second plurality of connecting electrodes; and

data holding means for holding bank selecting data, said data holding means having at least one input terminal coupled to at least some of said first plurality of electrodes and having at least one output terminal connected to a second predetermined portion of said memory address terminals of said first digital memory;

said data holding means being coupled to at least some of said third plurality of electrodes, wherein said data holding means has at least one data load controlling input, said data load controlling input being coupled to receive a read/write signal from said MPU via one of said third plurality of electrodes for loading bank selecting data received via said at least one input terminal.

16. External memory apparatus according to claim 15, wherein said data holding means provides, via said at least one output terminal, the most significant bits of a memory address to said address terminals of said first digital memory.

17. External memory apparatus which is removably connectable to a video game apparatus having a microprocessor (MPU), a picture processing unit (PPU) coupled to said MPU, and an edge connector, said MPU being connected to a MPU data bus and a MPU address bus and said PPU being connected to a PPU address bus and a PPU data bus, said MPU data bus, MPU address bus, PPU data bus and PPU address bus being connected to said edge connector, said external memory apparatus comprising:

an array of connecting electrodes connected to said edge connector when said external memory apparatus is loaded into said video game apparatus, said array of connecting electrodes including a first plurality of electrodes disposed to receive in use signals from said MPU address bus, and said MPU data bus, a second plurality of electrodes disposed to receive in use signals from said PPU address bus, and said PPU data bus, and a third plurality of electrodes disposed to receive in use memory accessing related signals generated by said microprocessor;

a first digital memory for storing at least one video game program, said first digital memory having address terminals, a first predetermined portion of said address terminals being coupled to at least some of said first plurality of connecting electrodes, said first digital memory having data terminals coupled to at least some of said first plurality of connecting electrodes, said first digital memory being divided into a plurality of memory banks;

a second digital memory for storing character data related to said video game program, said second digital memory being coupled to at least some of said second plurality of connecting electrodes; and

data holding means for holding bank selecting data, said data holding means having at least one input terminal coupled to at least some of said first plurality of electrodes and having at least one output terminal connected to a second predetermined portion of said memory address terminals of said first digital memory;

said data holding means being coupled to at least some of said third plurality of electrodes, wherein said data holding means is loaded with bank selecting data received via said at least one input terminal in response to at least one signal received via said third plurality of electrodes, wherein said data holding means has a clock input, said clock input being connected to a predetermined one of said third plurality of electrodes.

18. External memory apparatus according to claim 17, wherein said first digital memory has a chip enable input which is coupled to said predetermined one of said third plurality of electrodes.