Parallel vector processing system for individual and broadcast distribution of operands and control information

• US 5,226,171 A
• Filed: 12/03/1991
• Issued: 07/06/1993
• Est. Priority Date: 12/03/1984
• Status: Expired due to Term

• Current Assignee: Silicon Graphics International Corporation (Hewlett-Packard Enterprise Company)
• Original Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Inventors: Hall, William E., Stigers, Dale A., Decker, Leslie F.
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US07/802,643
• Time in Patent Office: 581 Days
• Field of Search: 395/800, 364/DIG. 1, 364/DIG. 2
• US Class Current: 712/9
• CPC Class Codes: G06F 15/8076 Details on data register access
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78

Abstract

A parallel processing system utilizes a plurality of simultaneously operable arithmetic units to provide matrix-vector products, with each of the arithmetic units implementing the matrix-vector product calculations for plural rows of a matrix stored as vectors in an arithmetic unit. A column of a second matrix is broadcast to the respective arithmetic units whereby the products may be developed in all the arithmetic units simultaneously. The broadcasting of the matrix elements is accomplished via a memory bus which may be employed for selectively or simultaneously accessing registers in the various arithmetic units whereby vector information may be written into memory addresses and calculation results retrieved therefrom.

Claims

1. A parallel vector processing system for individual and broadcast distribution of operands and control information, comprising:

a central processor unit;

a plurality of arithmetic units each having a vector data register, a scalar data register and a control register operable from said central processor unit for performing matrix-vector products;

bus means for intercoupling said central processor unit with said plurality of arithmetic units;

said vector data register, said scalar data register and said control register of each said arithmetic units being individually and directly addressable from said central processor unit using first memory mapped addresses of a contiguously addressable memory address space;

said vector data register, said scalar data register and said control register of all of said arithmetic units being collectively addressable using second memory mapped addresses from said contiguously addressable memory address space to receive the same data as an input operand in a simultaneous broadcast; and

said arithmetic units being further controllable from said central processor unit for beginning computation operations in response to directly writing to said registers of each of said arithmetic units.

2. The system according to claim 1 wherein said plurality of arithmetic units are controllable via said bus means to perform a matrix vector product defined by the expression y=A*x where y is a vector with m elements, A is a matrix with m rows and n columns, and x is a vector with n elements, an x vector being stored in said vector data register of each of said arithmetic units, and A being provided by rows and element by element within rows on said bus means to said plurality of said arithmetic units.

3. The system according to claim 2 wherein said vector data register of each of said plurality of arithmetic units stores plural vectors x and wherein an arithmetic unit receives an element of A and performs calculations relative to the plural vectors x before receiving another element of A.

4. The system according to claim 2 wherein a single element of y is accumulated in one of said plurality of arithmetic units as the sum of the element by element products of a row of A against the vector x, comprising the dot product, and wherein m dot products are completed involving the same vector x with successive rows of A.

5. The system according to claim 1 wherein each arithmetic unit of said plural arithmetic units is adapted to store a different x vector in said vector data register thereof for multiplication with rows of the A matrix supplied to said plural arithmetic units.

6. The system according to claim 5 wherein each arithmetic unit of said plural arithmetic units stores plural x vectors in said vector data register thereof for multiplication with rows of said A matrix.

7. The system according to claim 1 wherein said vector data register and said scalar register each being coupled for receiving data from said bus means;

said each of said arithmetic units further comprising a multiplier for receiving one input from said bus means and a second input from said vector data register; and

an adder for receiving one input from said multiplier and one input from said scalar register, the output of said adder being selectively provided to said scalar register.

8. The system according to claim 7 wherein said arithmetic unit includes a second, similarly coupled multiplier, and a second, similarly coupled adder.

9. The system according to claim 7 wherein said registers are adapted to store complex numbers with real and imaginary parts in successive locations, said multiplier and said adder being employed for performing successive multiplications and additions to provide complex results.

10. The system according to claim 1 wherein each arithmetic unit includes an index means for addressing said register means, said index means being coupled to said bus means, said index means being selectively incremented for accessing successive vector elements, and said index means being selectively addressable to provide addresses which access other than successive vector elements.

11. The system according to claim 1 wherein said vector data register and said scalar register each being coupled for receiving data from said bus means;

said each of said arithmetic units further comprising a multiplier for receiving one input from said bus means and a second input from said scalar data register; and

an adder for receiving one input from said multiplier and one input from said vector register, the output of said adder being selectively provided to a second vector register.

12. The system according to claim 1 wherein said vector data register and said scalar register each being coupled for receiving data from said bus means;

said each of said arithmetic units further comprising a multiplier for receiving one input from said bus means and a second input from said scalar data register; and

an adder for receiving one input from said multiplier and one input from said scalar register, the output of said adder being provided to a second vector register.