Current mode sample-and-hold circuit

• US 5,227,676 A
• Filed: 09/16/1991
• Issued: 07/13/1993
• Est. Priority Date: 09/16/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Larson, Tony R., Bahr, Allen A.
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US07/760,534
• Time in Patent Office: 666 Days
• Field of Search: 307/351, 307/353, 307/491, 307/494, 328/151
• US Class Current: 327/94
• CPC Class Codes: G11C 27/028 Current mode circuits, e.g. switched current memories

Abstract

The current mode sample-and-hold circuit includes a differential amplifier having a non-inverting input coupled to a first leg of a current mirror from which a first current to be sampled is drawn. An inverting input of the differential amplifier is coupled to its output and further coupled to a capacitor through a sample hold switch. The first current drawn from the first leg of the current mirror causes the capacitor to charge, through the differential amplifier. The charged capacitor is coupled to the current mirror and biases the current mirror so as to provide the required first current. Opening the sample hold switch causes the capacitor to maintain a bias level determined by the first current. The bias signal in turn causes a mirrored current flowing in a second leg of the current mirror to be maintained, even in the absence of the first current. Thus an input current is sampled and a corresponding output current is provided. The capacitor operates in a feedback loop for improving accuracy. Furthermore, the capacitor is isolated from both the input and output providing high frequency capability. Alternatively, the sample hold switch may be replaced by a diode for providing a peak detector function.

Claims

1. A monolithically integrated current mode sample-and-hold circuit, comprising:

amplifier means having an output for providing a gain, wherein said amplifier means is a differential amplifier having a first input which is an inverting input, and a second input which is a non-inverting input, wherein the first input is coupled to the output;

current mirror means having a first leg coupled to the said amplifier means from which a first current to be sampled is drawn, and having a second leg for providing a second current; and

charging means operatively coupled to the output of said amplifier means operating in a closed loop for storing a bias signal, the bias signal biasing said current mirror means such that the first leg supplies the first current, and the second leg continues to supply the second current, which is representative of the first current, after operatively decoupling said charging means from said amplifier means, wherein said charging means is a parasitic capacitance of said current mirror means.

2. The sample-and-hold circuit according to claim 1 further comprising a diode for operatively coupling said charging means to the differential amplifier output.

3. The sample-and-hold circuit according to claim 1 further comprising a switch for operatively coupling said charging means to the differential amplifier output.

4. The sample-and-hold circuit according to claim 3 wherein said switch is a transistor.

5. The sample-and-hold circuit according to claim 4 further comprising a second switch coupled to said charging means for resetting the bias signal thereby enabling the sample-and-hold circuit to sample another current.

6. The sample-and-hold circuit according to claim 1 wherein said charging means is a capacitor.

7. The sample-and-hold circuit according claim 6 wherein said current mirror further comprises:

a first transistor having a source coupled to a supply voltage, a gate coupled to said capacitor, and a drain coupled to said differential amplifier; and

a second transistor having a source coupled to the supply voltage, a gate coupled to said capacitor, and a drain coupled for providing the second current.

8. A monolithically integrated current mode sample-and-hold circuit, comprising:

amplifier means having an output for providing a gain;

current mirror means having a first leg coupled to the said amplifier means from which a first current to be sampled is drawn, and having a second leg for providing a second current; and

charging means operatively coupled to the output of said amplifier means operating in a closed loop for storing a bias signal, the bias signal biasing said current mirror means such that the first leg supplies the first current, and the second leg continues to supply the second current, which is representative of the first current, after operatively decoupling said charging means from said amplifier means, wherein said charging means is a parasitic capacitance of said current mirror means.

9. A monolithically integrated current mode sample-and-hold circuit, comprising:

a differential amplifier having an inverting input coupled to an output thereof, and a non-inverting input;

a current mirror having a bias terminal coupled to the output of said differential amplifier for receiving a bias signal, a first leg coupled to the non-inverting input for sinking a first current, and a second leg for providing a second current;

charging means coupled between the output of said differential amplifier and a supply voltage for carrying a charging current that flows through said differential amplifier for determining the magnitude of the bias signal; and

a first switch coupled to said charging means for resetting the bias signal.

10. The sample-and-hold circuit according to claim 9 further comprising a diode coupled between said charging means and the inverting input of said differential amplifier for causing the charging means to store a charge representing a peak magnitude of the first current.

11. The sample-and-hold circuit according to claim 9 further comprising a second switch coupled between said charging means and the output of said differential amplifier for disconnecting said differential amplifier, thereby sampling the first current.

12. The sample-and-hold circuit according to claim 11 wherein said second switch is a transistor.

13. The sample-and-hold circuit according to claim 12 wherein said charging means is a capacitor.

14. The sample-and-hold circuit according to claim 13 wherein said current mirror comprises:

a first transistor having a source coupled to a supply voltage, a gate coupled to said capacitor, and a drain coupled to said differential amplifier; and

a second transistor having a source coupled to the supply voltage, a gate coupled to said capacitor, and a drain coupled for providing the second current.

15. The sample-and-hold circuit according to claim 14 wherein said current mirror further comprises:

a third transistor having a source coupled to the supply voltage, a drain coupled to the drain of said first transistor, and a gate;

a fourth transistor having a source coupled to the supply voltage, a drain coupled to the drain of said second transistor, and a gate coupled to the gate of said third transistor;

a fifth transistor having a source coupled to the supply voltage, and a gate coupled to a drain and to the gate of said fourth transistor; and

a sixth transistor having a drain coupled to the drain of said fifth transistor, a gate coupled to the gate of said first transistor, and a source coupled to another supply voltage.

16. The sample-and-hold circuit according to claim 15 wherein said second and fourth transistors are a predetermined ratio of said first and third transistors, respectively.

17. The sample-and-hold circuit according to claim 9 wherein said charging means is a parasitic capacitance of said first transistor.

18. A monolithically integrated current mode sample-and-hold circuit, comprising:

a differential amplifier having an inverting input coupled to an output thereof, and a non-inverting input;

a current mirror having a bias terminal for receiving a bias signal, a first current carrying leg coupled to the non-inverting input for sinking a first current, and a second current carrying leg for providing a second current;

a first switch having a first terminal coupled to the output of said differential amplifier, and a second terminal coupled to the bias terminal;

a capacitor coupled between a first supply voltage and the bias terminal for carrying a charging current that flows through the differential amplifier and defines the magnitude of the bias signal; and

a second switch coupled across said capacitor for resetting the bias signal.

19. The current mode sample-and-hold circuit according to claim 18 wherein said current mirror further comprises:

a first transistor having a gate coupled to said bias terminal, a drain coupled to said differential amplifier, and a source; and

a second transistor having a gate coupled to said bias terminal, a drain coupled for providing the second current, and a source;

a third transistor having a source coupled to the first supply voltage, a drain coupled to the source of said first transistor, and a gate;

a fourth transistor having a source coupled to the first supply voltage, a drain coupled to the source of said second transistor, and a gate coupled to the gate of said third transistor;

a fifth transistor having a source coupled to the first supply voltage, and a gate coupled to a drain and to the gate of said fourth transistor; and

a sixth transistor having a drain coupled to the drain of said fifth transistor, a gate coupled to said bias terminal, and a source coupled to a second supply voltage.

20. The sample-and-hold circuit according to claim 19 wherein said second and fourth transistors are a predetermined ratio of said first and third transistors, respectively.

21. The sample-and-hold circuit according to claim 20 wherein the second current is substantially equal to the first current.

22. The sample-and-hold circuit according to claim 20 wherein the second current is a predetermined ratio of said first current.