Fast digital comparison circuit for fuzzy logic operations

• US 5,227,678 A
• Filed: 05/22/1991
• Issued: 07/13/1993
• Est. Priority Date: 05/22/1991
• Status: Expired due to Fees

• Current Assignee: Illinois Institute of Technology
• Original Assignee: Illinois Institute of Technology
• Inventors: Han, Jia-Yuan, Singh, Supreet
• Primary Examiner(s): HUDSPETH, DAVID R
• Application Number:
  US07/703,632
• Time in Patent Office: 783 Days
• Field of Search: 307/440, 307/443, 307/464, 307/450, 307/448, 307/451, 307/243, 307/494, 364/769
• US Class Current: 340/146.2
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: Y10S 706/90 Fuzzy logic

Abstract

A fast digital logic circuit for comparing two binary numbers and outputting the greater of the two is disclosed.

Claims

1. A circuit for comparing a first binary number to a second binary number, said first and second binary numbers having corresponding least significant bits, each of said first and second binary numbers comprising an equal plurality of blocks of bits, and generating an output binary number equal to either the greater or the lesser of said first binary number and said second binary number, said circuit comprising:

means for generating in parallel an intermediate plurality of bits, each of said plurality of bits corresponding to a respective pair of said blocks, each of said bits indicating which one of said pair of blocks is to be outputted; and

means responsive to said intermediate plurality of bits for generating an output number composed of said outputted blocks.

2. The circuit of claim 1 wherein each of said blocks are of equal size.

3. The circuit of claim 2 wherein each of said blocks consist of 1 bit.

4. The circuit of claim 2 wherein said outputted number is the greater of said first binary number and said second binary number.

5. The circuit of claim 2 wherein said outputted number is the lesser of said first binary number and said second binary number.

6. A circuit for comparing a first binary number to a second binary number, said first and second binary numbers having corresponding most significant bits consecutively followed to corresponding least significant bits, and generating an output binary number equal to the larger of said first binary number and said second binary number, comprising:

means for receiving said first binary numbers and said second binary number;

means for generating in parallel an intermediate plurality of bits corresponding to said bits of said first and second binary numbers, said intermediate plurality of bits indicating the highest significant bit of said first binary number that is greater than said corresponding bit of said second binary number; and

means responsive to said intermediate plurality of bits for generating in parallel an output binary number corresponding to said first and second binary numbers, said output binary number having bits progressing from said most significant bit equal to said corresponding bits of said second binary number until the bit at which said highest significant bit of said first binary number is greater than said corresponding bit of said second binary number, said remaining, lesser significant bits of said output binary number equal to said corresponding bits of said first binary number.

7. A digital circuit for comparing a first binary number to a second binary number and generating an output binary number equal to the greater of said first binary number and said second binary number, said first and second and output binary numbers having corresponding most significant bits consecutively followed to corresponding least significant bits, said circuit comprising:

a plurality of first digital implementations, each of said first digital implementations corresponding to a respective pair of said bits of said first binary number and said second binary number, each first digital implementation being set to a binary value of 1 if and only if the corresponding bits of said first binary number and said second binary number are equal;

a plurality of second digital implementations, each of said second digital implementations corresponding to a respective pair of bits of said first binary number and said second binary number, each said second digital implementation being set to a binary value of 1 if and only if said bit of said first binary number is greater than the corresponding bit of said second binary number;

a plurality of third digital implementations responsive to said first and second digital implementations, each third digital implementation corresponding to a bit of said output binary number, each of said third digital implementations indicating which of said bits of said first binary number and said second binary number are outputted, each of said third digital implementations being independent of the remaining third digital implementations; and

a plurality of fourth digital implementations responsive to said third digital implementation and said bits of said first binary number and said second binary number for producing said output binary number.

8. The circuit of claim 7 wherein said first binary number, said second binary number and said output binary number each comprise 16 bits.

9. The circuit of claim 7 wherein said fourth digital implementations comprise a plurality of multiplexors, each of said multiplexors corresponding to a respective pair of said bits of said first binary number and said second binary number, each pair of bits of said first binary number and said second binary number being inputs to the respective multiplexor, each of said multiplexors outputting a respective bit of said output binary number.

10. A digital circuit for comparing a first binary number to a second binary number and generating an output binary number equal to the lesser of said first binary number and said second binary number, said first and second and output binary numbers having corresponding most significant bits consecutively followed to corresponding least significant bits, said circuit comprising:

a plurality of first digital implementations, each of said first digital implementations corresponding to a respective pair of said bits of said first binary number and said second binary number, each first digital implementation being set to a binary value of 1 if and only if the corresponding bits of said first binary number and said second binary number are equal;

a plurality of second digital implementations, each of said second digital implementations corresponding to a respective pair of bits of said first binary number and said second binary number, each said second digital implementation being set to a binary value of 1 if and only if said bit of said first binary number is greater than the corresponding bit of said second binary number;

a plurality of third digital implementations responsive to said first and second digital implementations, each third digital implementation corresponding to a bit of said output binary number, each of said third digital implementations indicating which of said bits of said first binary number and said second binary number are outputted, each of said third digital implementations being independent of the remaining third digital implementations; and

a plurality of fourth digital implementations responsive to said third digital implementation and said bits of said first binary number and said second binary number for producing said output binary number.

11. The circuit of claim 10 wherein said first binary number, said second binary number and said output binary number comprise 16 bits.

12. The circuit of claim 10 wherein said fourth digital implementations comprise a plurality of multiplexors, each of said multiplexors corresponding to a respective pair of said bits of said first binary number and said second binary number, each pair of bits of said first binary number and said second binary number being inputs to the respective multiplexor, each of said multiplexors outputting a respective bit of said output binary number.