Video display apparatus including display device having fixed two-dimensional pixel arrangement

• US 5,227,882 A
• Filed: 09/25/1991
• Issued: 07/13/1993
• Est. Priority Date: 09/29/1990
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Kato, Naoki
• Primary Examiner(s): Kostak, Victor R.
• Application Number:
  US07/765,527
• Time in Patent Office: 657 Days
• Field of Search: 358/140, 358/230, 358/241, 358/56, 358/148, 358/181, 358/160
• US Class Current: 348/571
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0276 for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
• CPC Class Codes: G09G 2340/0414 Vertical resolution change
• CPC Class Codes: G09G 2340/0421 Horizontal resolution change
• CPC Class Codes: G09G 2340/0442 Handling or displaying different aspect ratios, or changing the aspect ratio
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H04N 7/0122 the input and the output signals having different aspect ratios

Abstract

A video display apparatus includes an LCD device of the active matrix type and an image memory having an arrangement and storage capacity corresponding to the two-dimensional pixel arrangement thereof. A necessary processing such as conversion of the number of scanning lines, time-base companding in the horizontal direction and so on is applied to the inputted video signal according to the format thereof and then the inputted video signal is written into the two-dimensional arrangement of the image memory. The data written into the image memory is read out by a clock of a fixed frequency within a period shorter than the writing period asynchronously with the writing operation. Then, the LCD is driven by the read data and an image is displayed on the pixel arrangement.

Claims

1. A video display apparatus comprising:

a display device having a fixed two-dimensional pixel arrangement;

an image memory capable of storing a video signal with a two-dimensional arrangement corresponding the two-dimensional pixel arrangement of said display device and capable of asynchronous writing and reading operations;

receiving means for selectively receiving a video signal to be displayed among video signals of a plurality of formats;

extracting means for extracting horizontal and vertical synchronizing signals from said received video signal;

first clock generating means for generating at least one kind of clock having a phase synchronous with that of said extracted horizontal synchronizing signal and having a frequency selected according to the format of said received video signal;

processing and writing means for processing said received video signal in response to said clock and writing said video signal into said image memory so as to place an effective display region of said video signal within the two-dimensional pixel arrangement of said image memory;

second clock generating means for generating a clock of a fixed frequency;

reading means triggered by said extracted vertical synchronizing signal for reading the contents of said image memory within a fixed period in response to the clock of said fixed frequency asynchronously with the writing operation, said fixed period in which the contents of said image memory are read out is set shorter than the shortest one among the vertical periods of said video signals of the plurality of formats; and

driving means for driving the display device so as to display an image on the two-dimensional pixel arrangement of said display device according to said read contents of the image memory.

2. The video display apparatus according to claim 1, wherein said image memory has an arrangement and storage capacity corresponding to said two-dimensional pixel arrangement for each video component constituting each video signal.

3. The video display apparatus according to claim 1, wherein the relative phase relationship of the start. between the asynchronous writing and reading operations of said image memory is fixed.

4. The video display apparatus according to claim 1, further comprising format determining means for determining the format of the received video signal.

5. The video display apparatus according to claim 4, wherein said processing and writing means includes means for writing said received video signal directly into said image memory according to the result of the determination by said format determining means.

6. The video display apparatus according to claim 4, wherein said processing and writing means includes means for performing scanning line number conversion and time-base companding in the horizontal direction of said received video signal according to the result of the determination by said format determining means.

7. The video display apparatus according to claim 6, wherein said conversion of the number of scanning lines and time-base companding in the horizontal direction are performed by writing and reading the video signal into/from a line memory using a plurality of clocks having periods of a prescribed ratio.

8. The video display apparatus according to claim 1, wherein said reading means includes means for applying a fixed signal processing to the video signal read from said image memory.

9. The video display apparatus according to claim 1, wherein said display device comprises an LCD device.

10. The video display apparatus according to claim 9, wherein said LCD device comprises an LCD device of an active matrix type.

11. A video display apparatus comprising:

a display device having a fixed two-dimensional pixel arrangement;

an image memory capable of storing a video signal with a two-dimensional arrangement corresponding to the two-dimensional pixel arrangement of said display device and capable of asynchronous writing and reading operations;

receiving means for selectively receiving a video signal to be displayed among video signals of a plurality of formats;

extracting means for extracting horizontal and vertical synchronizing signals from said received video signal;

first clock generating means for generating at least one kind of clock having the phase synchronous with that of said extracted horizontal synchronizing signal and having a frequency selected according to the format of said received video signal;

processing and writing means for processing said received video signal in response to said clock and writing said video signal into said image memory so as to place an effective display region of said video signal within the two-dimensional pixel arrangement of said image memory;

second clock generating means for generating a clock of a fixed frequency;

reading means triggered by said extracted vertical synchronizing signal for reading the contents of said image memory within a fixed period in response to the clock of said fixed frequency asynchronously with the writing operation, said reading means including applying means for applying a fixed signal processing to the video signal read from said image memory; and

driving means for driving the display device so as to display an image on the two-dimensional pixel arrangement of said display device according to said read contents of the image memory.

12. A method for displaying video signals of a plurality of formats on a display device having a fixed two-dimensional pixel arrangement, comprising the steps of:

(a) storing a video signal with a two-dimensional arrangement corresponding to the two-dimensional pixel arrangement of the display device in an image memory which is capable of asynchronous writing and reading operations;

(b) selectively receiving a video signal to be displayed from among the video signals of the plurality of formats;

(c) extracting horizontal and vertical synchronizing signals from said video signal received at said step (b);

(d) generating at least one kind of clock having a phase synchronous with that of said horizontal synchronizing signal extracted at said step (c) and having a frequency selected according to the format of said video signal received at said step (b);

(e) processing said video signal received at said step (b) in response to said clock generated at said step (d);

(f) writing said video signal processed at said step (e) into said image memory so as to place an effective display region of said video signal within the two-dimensional pixel arrangement of said image memory;

(g) generating a clock of a fixed frequency;

(h) reading the contents of said image memory, triggered by said vertical synchronizing signal extracted at said step (c), within a fixed period in response tot he clock of said fixed frequency asynchronously with the writing operation;

(i) setting said fixed period in which the contents of said image memory are read out shorter than the shortest one among the vertical periods of the video signals of the plurality of formats; and

(j) driving the display device so as to display an image on the two-dimensional pixel arrangement of the display device according to the contents read out of said image memory.

13. The method for displaying video signals according to claim 12, wherein said image memory has an arrangement and storage capacity corresponding to the two-dimensional pixel arrangement for each video component constituting each video signal.

14. The method for displaying video signals according to claim 13, further comprising the step of fixing the relative phase relationship of the start between the asynchronous writing and reading operations of said image memory.

15. The method for displaying video signals according to claim 12, further comprising the step of determining the format of said video signal received at said step (b).

16. The method for displaying video signals according to claim 15, wherein said step (f) further includes the step of writing said video signal received at said step (b) into said image memory according to the result of said step of determining the format of said video signal received at said step (b).

17. The method for displaying video signals according to claim 15, wherein said step (f) further includes the step of performing scanning line number conversion and time-base companding in the horizontal direction of said video signal received at said step (b) according to the result of said step of determining the format of said video signal received at said step (b).

18. The method for displaying video signals according to claim 17, wherein the conversion of the number of scanning lines and time-base companding in the horizontal direction are performed by writing and reading the video signal into and from a line memory using a plurality of clocks having periods of a prescribed ratio.

19. The method for displaying video signals according to claim 12, wherein the display device comprises an LCD device.

20. A method for displaying video signals of a plurality of formats on a display device having a fixed two-dimensional pixel arrangement, comprising the steps of:

(a) storing a video signal with a two-dimensional arrangement corresponding to the two-dimensional pixel arrangement of the display device in an image memory which is capable of asynchronous writing and reading operations;

(b) selectively receiving a video signal to be displayed from among the video signals of the plurality of formats;

(c) extracting horizontal and vertical synchronizing signals from said video signal received at said step (b);

(d) generating at least one kind of clock having a phase synchronous with that of said horizontal synchronizing signal extracted at said step (c) and having a frequency selected according to the format of said video signal received at said step (b);

(e) processing said video signal received at said step (b) in response to said clock generated at said step (d);

(f) writing said video signal processed at said step (e) into said image memory so as to place an effective display region of said video signal within the two-dimensional pixel arrangement of said image memory;

(g) generating a clock of a fixed frequency;

(h) reading the contents of said image memory, triggered by said vertical synchronizing signal extracted at said step (c), within a fixed period in response to the clock of said fixed frequency asynchronously with the writing operation;

(i) applying a fixed signal processing to the video signal read from said image memory; and

(j) driving the display device so as to display an image on the two-dimensional pixel arrangement of the display device according to the contents read out of said image memory.