Source-level in-circuit software code debugging instrument

• US 5,228,039 A
• Filed: 05/09/1990
• Issued: 07/13/1993
• Est. Priority Date: 05/09/1990
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Applied Microsystems Corporation
• Inventors: Knoke, Robin L., Johnson, Marvin T.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): LO, ALLEN
• Application Number:
  US07/521,261
• Time in Patent Office: 1,161 Days
• Field of Search: 371/19, 371/16.2, 371/16.1
• US Class Current: 714/28
• CPC Class Codes: G06F 11/3652 in-circuit-emulation [ICE] arrangements

Abstract

A source-level run-time software code debugging instrument (10) includes a target access probe ("TAP") (12) and a communications adapter ("COMDAP") (14) that process emulation commands provided by source-level debugging software operating on a host computer. The TAP includes a TAP CPU (28) that receives target CPU input signals and delivers target CPU output signals for controlling the execution of software code by the target circuit in accordance with command signals provided by the host computer. The TAP also includes a programmable logic cell array (24) and a RAM (34). The TAP logic cell array routes command and data signals to and from the TAP CPU, and the RAM stores an in-circuit emulation ("ICE") program used by the TAP to operate the target circuit. The COMDAP is physically separate from the TAP and provides an interface between the host computer and the TAP. The COMDAP includes a programmable logic cell array (44) and an EPROM (46). The COMDAP logic cell array routes command and data signals to and from the COMDAP, and the EPROM stores the commands for configuring the signal paths within the TAP and COMDAP logic cell arrays and stores the TAP ICE program. A flat cable assembly (16) provides a high-speed signal communications link between the TAP and the COMDAP. The TAP uses certain microprocessor signal features and source-level debugging software that runs on the host computer to provide a software engineer with a fully transparent window into the internal functioning of the TAP CPU while executing code in the target circuit environment.

Claims

1. An instrument for testing and verifying the operational performance of a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the instrument comprising:

target access probe ("TAP") means including a TAP CPU receiving target CPU input signals and delivering target CPU output signals for controlling the execution of software code on the target computer system in accordance with command signals provided by a host analysis code source, the TAP means including TAP signal routing means for routing the command signals to the TAP CPU;

a communications adapter ("COMDAP") that provides an interface between the host analysis code source and the TAP means, the COMDAP including COMDAP memory means having memory sites that store information for configuring signal paths within the COMDAP; and

data communication linking means for providing a data communication link between the TAP means and the COMDAP.

2. The instrument of claim 1 in which the COMDAP memory means is of a reprogrammable type, thereby providing a capability of storing information for configuring different signal paths within the COMDAP to enable writing command signals delivered by host analysis code sources of different types.

3. The instrument of claim 1 in which the TAP signal routing means comprises a TAP logic cell array and in which each of the TAP logic cell array and the COMDAP memory means is of a reprogrammable type, the COMDAP memory means being adaptable for storing information for configuring signal paths within the TAP logic cell array.

4. The instrument of claim 3 in which the TAP means further comprises a TAP memory having memory sites that store instructions carried by command signals delivered by the COMDAP and routed through the TAP logic cell array.

5. The instrument of claim 4 in which the TAP memory is of a random access memory type.

6. The instrument of claim 4 in which the COMDAP memory means and the TAP memory are in signal communication with each other and the instructions stored in the COMDAP memory sites are transferred to the TAP CPU at the time electrical power is initially applied to the instrument.

7. The instrument of claim 1 in which the TAP means and COMDAP are physically separate and in which the data communication linking means includes multiple electrically insulated conductors that carry the command signals between the TAP means and the COMDAP.

8. The instrument of claim 7 in which the conductors are configured to form a flat cable assembly.

9. A target access probe ("TAP") for connecting to a target circuit that includes a target CPU communicating with a target program memory having memory sites that store main program instructions for exercising of target circuit components, the target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the TAP testing and verifying the operational performance of the target circuit in response to host command signals provided by a host computer in the electrical absence of the target CPU and comprising:

a TAP CPU receiving target CPU input signals at the input terminal positions and delivering target CPU output signals at the output terminal positions;

in-circuit emulation ("ICE") means including ICE program memory sites that store ICE program instructions and communicating with the TAP CPU for producing the target CPU output signals in accordance with the ICE program instructions executed by the TAP CPU in response to the host command signals, the ICE program instructions including an instruction for transferring operational control of the TAP CPU from the target program to the ICE program and instructions for reading information from or writing information into target program memory sites;

a TAP signal routing integrated circuit for configuring signal paths within the TAP; and

input and output signal link means for providing a signal link to and from the host computer for the target CPU input and output signals;

whereby the ICE means resides wholly outside of the target circuit and the delivery of the target CPU input signals to the corresponding target CPU input terminal positions and the delivery of the target CPU output signals to the corresponding target CPU output positions in response to the host command signals provide a capability for testing and verifying the performance of the target circuit in accordance with the ICE program instructions independently of the target program stored therein.

10. The TAP of claim 9 in which the TAP CPU produces an ICE address strobe signal that enables access to the ICE program memory sites.

11. The TAP of claim 10 in which the ICE program memory sites respond to the receipt of the ICE address strobe signal by delivering an ICE ready signal to the TAP CPU.

12. The TAP of claim 9 in which the TAP CPU produces a break signal that suspends execution of instructions stored in the main program memory sites and commences execution of instructions stored in the ICE program memory sites.

13. The TAP of claim 9 in which the TAP signal routing integrated circuit is of a programmable type.

14. The TAP of claim 9 in which the TAP signal routing integrated circuit comprises a logic cell array.

15. The TAP of claim 14 in which the TAP signal routing integrated circuit comprises a reprogrammable logic cell array.

16. An instrument for testing and verifying the operational performance of a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the instrument comprising:

target access probe ("TAP") means including a TAP CPU receiving target CPU input signals and delivering target CPU output signals for controlling the execution of software code on the target computer system in accordance with command signals provided by a host analysis code source;

a communications adapter ("COMDAP") that cooperates with the TAP means to provide an interface between the host analysis code source and the TAP means, the COMDAP including a COMDAP memory having memory sites that store information for configuring signal paths within the COMDAP; and

data communication linking means for providing a data communication link between the TAP means and the COMDAP, the data communication link including handshake signals that indicate to the COMDAP whether the TAP means is available to provide data to the COMDAP and to the TAP means whether the COMDAP is available to receive data from the TAP means.

17. An instrument for testing and verifying the operational performance of a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the instrument comprising:

target access probe ("TAP") means including a TAP CPU receiving target CPU input signals and delivering target CPU output signals for controlling the execution of software code on the target computer system in accordance with command signals provided by a host analysis code source;

a communications adapter ("COMDAP") that cooperates with the TAP means to provide an interface between the host analysis code source and the TAP means;

a signal routing integrated circuit operatively associated with one of the TAP means and COMDAP to configure signal paths within the one of the TAP means and COMDAP; and

data communication linking means for providing a data communication link between the TAP means and the COMDAP, the data communication link including handshake signals that indicate to the COMDAP whether the TAP means is available to provide data to the COMDAP and to the TAP means whether the COMDAP is available to receive data from the TAP means.

18. The instrument of claim 17 in which the signal routing integrated circuit is of a programmable type.

19. The instrument of claim 18 in which the signal routing integrated circuit comprises a logic cell array of a reprogrammable type.

20. The instrument of claim 17 in which the signal routing integrated circuit comprises a logic cell array.

21. An instrument for testing and verifying the operational performance of a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the instrument comprising:

target access probe ("TAP") means including a TAP CPU receiving target CPU input signals and delivering target CPU output signals for controlling the execution of software code on the target computer system in accordance with command signals provided by a host analysis code source, the TAP means further including TAP signal path configuring memory sites that store information for configuring signal paths within the TAP means;

a communications adapter ("COMDAP") that cooperates with the TAP means to provide an interface between the host analysis code source and the TAP means; and

data communication linking means for providing a data communication link between the TAP means and the COMDAP, the data communication link including handshake signals that indicate to the COMDAP whether the TAP means is available to provide data to the COMDAP and to the TAP means whether the COMDAP is available to receive data from the TAP means.

22. A target access probe ("TAP") for connecting to a target circuit that includes a target CPU communicating with a target program memory having memory sites that store main program instructions for exercising of target circuit components, the target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the TAP testing and verifying the operational performance of the target circuit in response to host command signals provided by a host computer in the electrical absence of the target CPU and comprising:

a TAP CPU receiving target CPU input signals at the input terminal positions and delivering target CPU output signals at the output terminal positions;

in-circuit emulation ("ICE") means including ICE program memory sites that store ICE program instructions and communicating with the TAP CPU for producing the target CPU output signals in accordance with the ICE program instructions executed by the TAP CPU in response to the host command signals, the ICE program instructions including an instruction for transferring operational control of the TAP CPU from the target program to the ICE program and instructions for reading information from or writing information into target program memory sites;

a TAP signal path configuration memory having memory sites that store information for configuring signal paths within the TAP; and

input and output signal link means for providing a signal link to and from the host computer for the target CPU input and output signals;

whereby the ICE means resides wholly outside of the target circuit and the delivery of the target CPU input signals to the corresponding target CPU input terminal positions and the delivery of the target CPU output signals to the corresponding target CPU output positions in response to the host command signals provide a capability for testing and verifying the performance of the target circuit in accordance with the ICE program instructions independently of the target program stored therein.

23. An instrument for testing and verifying the operational performance of a target computer system in the electrical absence of a target CPU having input and output terminal positions at which respective specified target CPU input and output signals appear, the instrument comprising:

target access probe ("TAP") means including a TAP CPU receiving target CPU input signals and delivering target CPU output signals for controlling the execution of software code on the target computer system in accordance with command signals provided by a host analysis code source;

a communications adapter ("COMDAP") that provides an interface between the host analysis code source and the TAP means;

a signal routing integrated circuit operatively associated with one of the TAP means and COMDAP to configure signal paths within the one of the TAP means and COMDAP; and

data communication linking means for providing a data communication link between the TAP means and the COMDAP.

24. The instrument of claim 23 in which the signal routing integrated circuit is of a programmable type.

25. The instrument of claim 24 in which the signal routing integrated circuit includes a reprogrammable logic cell array.

26. The instrument of claim 25 in which the TAP means further comprises a TAP signal path configuration memory including memory sites that store information for configuring signal paths within the TAP.

27. The instrument of claim 23 in which the signal routing integrated circuit includes a logic cell array.

28. The instrument of claim 23 in which the TAP means and COMDAP are physically separate and in which the data communication linking means includes multiple electrically insulated conductors that carry the command signals between the TAP means and the COMDAP.

29. The instrument of claim 23 in which the TAP means further comprises a TAP instruction memory having memory sites that store instructions carried by command signals.

30. The instrument of claim 29 in which the TAP memory is of a random access memory type.

31. The instrument of claim 23 in which the signal routing integrated circuit is operatively associated with the TAP means.

32. The instrument of claim 23 in which the COMDAP includes a COMDAP memory having memory sites that store information for configuring the signal paths within the COMDAP.