Data processor with selectively enabled and disabled branch prediction operation

• US 5,228,131 A
• Filed: 03/06/1991
• Issued: 07/13/1993
• Est. Priority Date: 02/24/1988
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ueda, Tatsuya, Yoshida, Toyohiko
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US07/666,502
• Time in Patent Office: 860 Days
• Field of Search: 395/DIG. 1, 395/DIG. 2, 395/375
• US Class Current: 712/240
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage

Abstract

The data processor related to the invention enables to designate whether the branch prediction mechanism itself should be activated or not for a conditional branch instruction, and the data processor enables to initialize branch history as required and also designates activation or inactivation of the branch prediction mechanism by setting a specific value to a specific bit of an exclusive usable register by software means. Also when a specific instruction is executed, the data processor automatically clears the branch history. As a result, in the event when the data processing efficiency is adversely declined by application of branch prediction mechanism or when monitoring external address bus, the branching prediction mechanism can be inactivated by setting the predetermined value to the exclusive usable register. Likewise, when the reliability of the branch history lowers due to such as variation in the program running condition, the data processor is capable of clearing the branch history by writing a specific value into the exclusive usable register, and when executing a specific instruction which varies the program executing condition, branch history is automatically cleared.

Claims

1. A pipeline processor having a series of processing stages for processing a set of instructions, the processor comprising:

means for detecting a conditional branch instruction;

means for selectively predicting either one of satisfaction or non-satisfaction of a prescribed condition of said conditional branch instruction prior to execution of said conditional branch instruction; and

means for controlling the selectivity of said predicting means, said controlling means having a first state and a second state, said controlling means during said first state enabling said predicting means to predict whether said condition is satisfied, said controlling means during said second state disabling said predicting means to preclude prediction of whether said prediction is satisfied; and

wherein the state of said controlling means is defined by an instruction to be either one of said first state or said second state.

2. The processor of claim 1 further comprising a branch history table for storing a branch history of conditional branch instructions, said predicting means accessing said branch history table during said first state to predict whether said condition is satisfied.

3. The processor of claim 2 in which said branch history table is cleared in response to a change in a program executing condition.

4. A pipeline processor having a series of processing stages for processing a set of instructions, the processor comprising

means for detecting a conditional branch instruction;

means for selectively predicting either one of satisfaction or non-satisfaction of a prescribed condition of said conditional branch instruction prior to execution of said conditional branch instruction;

means for controlling the selectivity of said predicting means, said controlling means having a first state and a second state, said controlling means during said first state enabling said predicting means to predict whether said condition is satisfied, said controlling means during said second state disabling said predicting means to preclude prediction of whether said prediction is satisfied; and

a branch history table for storing a branch history of conditional branch instructions, said predicting means accessing said branch history table during said first state to predict whether said condition is satisfied.

5. The processor of claim 4 in which the state of said controlling means is defined by an instruction to be either one of said first state or said second state.

6. The processor of claim 5 in which said branch history table is cleared in response to a change in a program executing condition.

7. The data processor of claim 4 wherein said branch history table stores prespecified prediction values which are all false and that a desired prespecified pattern indicates no branch prediction such that said branch prediction means predicts processing in a particular order when in said first state.