Dry process for removal of undesirable oxide and/or silicon residues from semiconductor wafer after processing
First Claim
1. In a process for forming polysilicon lines over an oxide layer on an integrated circuit structure formed on a semiconductor wafer wherein a polysilicon layer on said oxide layer is patterned by etching through said polysilicon layer down to said underlying oxide layer whereby silicon-rich oxide residues from said etching step are deposited on the sidewalls of said polysilicon lines, the improvement which comprises:
- removing said silicon-rich oxide residues from said sidewalls by contacting said residues for from about 5 to about 60 seconds with an etchant gas containing at least 40 volume % NF3 in an etchant chamber while maintaining said semiconductor wafer in said etchant chamber within a temperature range of from about -25°
C. to about 150°
C.
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Accused Products
Abstract
A process is disclosed for the removal of residual oxide and/or silicon materials from a semiconductor wafer such as silicon-rich oxide residues or polysilicon stringers from the sidewalls of lines or steps formed over semiconductor wafers during the construction of integrated circuit structures without removing the wafer from the vacuum apparatus used in forming the lines on the wafer using a high pressure magnetically enhanced plasma etch using an NF3 -containing gas containing at least about 40 volume % NF3 as the etchant gas.
51 Citations
23 Claims
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1. In a process for forming polysilicon lines over an oxide layer on an integrated circuit structure formed on a semiconductor wafer wherein a polysilicon layer on said oxide layer is patterned by etching through said polysilicon layer down to said underlying oxide layer whereby silicon-rich oxide residues from said etching step are deposited on the sidewalls of said polysilicon lines, the improvement which comprises:
- removing said silicon-rich oxide residues from said sidewalls by contacting said residues for from about 5 to about 60 seconds with an etchant gas containing at least 40 volume % NF3 in an etchant chamber while maintaining said semiconductor wafer in said etchant chamber within a temperature range of from about -25°
C. to about 150°
C. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
- removing said silicon-rich oxide residues from said sidewalls by contacting said residues for from about 5 to about 60 seconds with an etchant gas containing at least 40 volume % NF3 in an etchant chamber while maintaining said semiconductor wafer in said etchant chamber within a temperature range of from about -25°
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16. In a process for forming polysilicon lines on an oxide layer formed over underlying steps on an integrated circuit structure formed on a semiconductor wafer wherein a polysilicon layer on said oxide layer is patterned by etching through said polysilicon layer down to said underlying oxide layer and wherein polysilicon stringers remain on said oxide layer between adjacent polysilicon lines formed from said polysilicon layer at a position where said oxide layer passes over said underlying steps after said etching step to form said polysilicon lines, the improvement which comprises:
- removing said polysilicon stringers on said oxide layer by contacting said stringers for from about 5 to about 120 seconds with an etchant gas containing at least 40 volume % NF3 in an etchant chamber while maintaining said semiconductor wafer in said etchant chamber within a temperature range of from about -25°
C. to about 150°
C.
- removing said polysilicon stringers on said oxide layer by contacting said stringers for from about 5 to about 120 seconds with an etchant gas containing at least 40 volume % NF3 in an etchant chamber while maintaining said semiconductor wafer in said etchant chamber within a temperature range of from about -25°
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17. An improvement in the process for forming polysilicon lines over an oxide layer on an integrated circuit structure formed on a semiconductor wafer wherein a polysilicon layer on said oxide layer is patterned by etching through said polysilicon layer down to said underlying oxide layer whereby silicon-rich oxide residues from said etching step are deposited on the sidewalls of said polysilicon lines, the improvement comprising removing said silicon-rich oxide residues from said sidewalls by the steps of:
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(a) mounting said wafer on a cathode capable of maintaining a wafer temperature of from about -5°
C. to about 150°
C. in a vacuum etch chamber maintained at a pressure within a range of from about 20 milliTorr to about 1 Torr;b) flowing into said etch chamber at a rate equivalent to from about 10 to about 500 sccm flowing into a 1200 cc. vacuum chamber, an NF3 -containing etchant gas containing at least 40 volume % NF3 with the balance consisting essentially of one or more gases selected from the group consisting of argon, helium, oxygen, SF6, Cl2, and CF4 ; c) igniting a plasma in said chamber and maintaining it at a power level ranging from about 50 to about 400 watts while said NF3 -containing etchant gas is flowing into said chamber; d) immersing said wafer in said chamber in a magnetic field parallel to the plane of said wafer at a field strength of at least about 25 gauss during said etch; and e) etching said sidewalls of said polysilicon lines for a period of from about 5 to about 60 seconds to remove said silicon-rich oxide residues from said sidewalls of said polysilicon lines. - View Dependent Claims (18, 19, 20, 21)
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22. An improvement in the process for forming polysilicon lines over an oxide layer on an integrated circuit structure formed on a semiconductor wafer wherein a polysilicon layer on said oxide layer is patterned into raised polysilicon lines on said integrated circuit structure by etching through said polysilicon layer down to said underlying oxide layer whereby silicon-rich oxide residues from said etching step are deposited on the sidewalls of said polysilicon lines, the improvement comprising removing said silicon-rich oxide residues from said sidewalls by the steps of:
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a) mounting said wafer on a cathode capable of maintaining a wafer temperature of from about 5°
C. to about 65°
C. in a vacuum chamber maintained at a pressure within a range of from about 100 milliTorr to about 400 milliTorr;b) flowing into said chamber at a rate equivalent to from about 150 to about 200 sccm flowing into a 1200 cc. vacuum chamber, an NF3 -containing etchant gas containing at least 50 volume % NF3 with the balance consisting essentially of one or more gases selected from the group consisting of argon, helium, oxygen, SF6, Cl2, and CF4 ; c) igniting a plasma in said chamber and maintaining it at a power level ranging from about 50 to about 400 watts while said NF3 gas is flowing into said chamber; d) immersing said wafer in said chamber in a magnetic field parallel to the plane of said wafer at a field strength of from about 25 gauss to about 150 gauss during said etch; and e) maintaining said etch conditions for a time period of from about 5 to about 60 seconds; to thereby remove said silicon-rich oxide residues from said sidewalls of said polysilicon lines.
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23. In a process for forming overlying polysilicon lines on an oxide layer formed over underlying polysilicon lines on an integrated circuit structure formed on a semiconductor wafer wherein a polysilicon layer on said oxide layer is patterned by etching through said polysilicon layer down to said underlying oxide layer and wherein polysilicon stringers remain on said oxide layer between adjacent overlying polysilicon lines formed from said polysilicon layer at a position where said oxide layer passes over said underlying polysilicon lines after said etching step to form said overlying polysilicon lines, the improvement which comprises:
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a) mounting said wafer on a cathode capable of maintaining a wafer temperature of from about 5°
C. to about 65°
C. in a vacuum chamber maintained at a pressure within a range of from about 100 milliTorr to about 400 milliTorr;b) flowing into said chamber at a rate equivalent to from about 10 to about 500 sccm flowing into a 1200 cc. vacuum chamber, an NF3 -containing etchant gas containing at least 50 volume % NF3 with the balance consisting essentially of one or more gases selected from the group consisting of argon, helium, oxygen, SF6, Cl2, and CF4 ; c) igniting a plasma in said chamber and maintaining it at a power level ranging from about 50 to about 400 watts while said NF3 gas is flowing into said chamber; d) immersing said wafer in said chamber in a magnetic field parallel to the plane of said wafer at a field strength of from about 25 gauss to about 150 gauss during said etch; and e) maintaining said etch conditions for a time period of from about 5 to about 120 seconds.
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Specification