Method of making extended silicide and external contact

• US 5,229,307 A
• Filed: 12/19/1990
• Issued: 07/20/1993
• Est. Priority Date: 01/22/1985
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Burton, Gregory N., Kapoor, Ashok K., Vora, Madhukar
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TRINH, LOC
• Application Number:
  US07/630,473
• Time in Patent Office: 944 Days
• Field of Search: 437/31, 437/32, 437/33, 437/34, 437/41, 437/200, 437/192, 437/189, 148/DIG. 124, 357/34, 357/35
• US Class Current: 438/234
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76889 by forming silicides of refractory metals
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53271 containing semiconductor material, e.g. polysilicon
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

There is disclosed a process for making high performance bipolar and high performance MOS devices on the same integrated circuit die. The process comprises forming isolation islands of epitaxial silicon surrounded by field oxide and forming MOS transistors having polysilicon gates in some islands and forming bipolar transistors having polysilicon emitters in other islands. Insulating spacers are then formed around the edges of the polysilicon electrodes by anisotropically etching a layer of insulation material, usually thermally grown silicon dioxide covered with additional oxide deposited by CVD. A layer of refractory metal, preferably titanium covered with tungsten, is then deposited and heat treated at a temperature high enough to form only titanium disilicide to form silicide over the tops of the polysilicon electrodes and on top of the bases, sources and drains. Regions of this refractory metal are then masked off such that the electrical contact with the silicide is preserved and so that the refractory metal extends to a contact pad position external to the isolation island. Metal posts can be formed at the contact pad positions and a layer of planarized insulation material is formed so as to leave only the tops of the posts exposed. A layer of metal can then be deposited and etched to make electrical contact with tops of the posts.

Claims

1. A process for forming an external base contact for a bipolar transistor having a base region formed in an island of semiconductor material which is electrically isolated from its surrounding semiconductor material comprising the steps:

forming a layer of metal over the exposed silicon of said base region;

heat treating said metal to form silicide which is self aligned with the perimeter of said base region;

forming an etch protection layer overlapping the edge of said silicide aligned with the edge of said isolation island and the portion of said metal layer adjacent to said edge and in electrical contact with said silicide;

etching away portions of said metal layer not so protected.

2. The process of claim 1 further comprising the step of also forming said etch protection layer over a portion of said metal layer which is external to said base region and in electrical contact with said silicide.

3. The process of claim 1 further comprising the steps of forming an insulating layer over the portions of said metal which were not etched away and forming a base contact window in said insulating layer over said metal in a location external to the perimeter of said base region.

4. The process of claim 1 further comprising the steps of forming an emitter contact electrically coupled to an emitter region in said base region and forming an emitter contact insulating layer on the sides of said emitter contact to prevent said silicide over said base region from electrically contacting said emitter contact.

5. The process of claim 4 wherein said emitter contact insulating layer is formed by the steps of forming an insulating layer over said base regions before said silicide is formed and over said emitter contact and then anisotropically etching away the insulating layer to leave a self aligned insulating layer on the sides of the emitter contact but no insulating layer on the base regions or the top of the emitter contact.

6. The process of claim 5 wherein said emitter contact is formed of polysilicon and said metal layer is also formed in the exposed top of said emitter contact before heat treatment so that silicide is also formed on the top of said emitter contact.

7. A process of forming an external base contact for a bipolar transistor having a base region formed in an island of semiconductor material which is electrically isolated from its surrounding semiconductor material comprising the steps of:

forming a layer of metal over the exposed silicon of said base region;

heat treating said metal to form silicide which is self aligned with the perimeter of said base region;

forming an etch protection layer over portions of said metal layer not turned into silicide during said heat treatment;

etching away portions of said metal layer not turned into silicide during said heat treatment that are unprotected by said etch protection layer;

forming an insulating layer over said silicide;

forming a contact window in said insulating layer which partially overlaps the silicide covering said base region;

forming a conductive layer over said contact window which fills said contact window and makes electrical contact with said silicide.

8. The process of claim 7 further comprising the steps of forming an emitter contact electrically coupled to an emitter region in said base region and forming an emitter contact insulating layer on the sides of said emitter contact to prevent said silicide over said base region from electrically contacting said emitter contact.

9. The process of claim 8 wherein said emitter contact insulating layer is formed by the steps of forming an insulating layer over said base region before said silicide is formed and over said emitter contact and then anisotropically etching away the insulating layer to leave a self aligned insulating layer on the sides of the emitter contact but no insulating layer on the base region or the top of the emitter contact.

10. The process of claim 9 wherein said emitter contact is formed of polysilicon and said metal layer is also formed on the exposed tops of said emitter contact before heat treatment so that silicide is also formed in the top of said emitter contact.

11. The process of claim 10 further comprising the step of forming an insulating layer separating said emitter contact from said emitter region.

12. A process for forming a semiconductor structure comprising the steps of:

forming on a semiconductor substrate doped with impurities of a first type, an epitaxially grown layer of semiconductor doped with impurities of a second type;

forming an isolation island in said epitaxially grown layer to electrically isolate the island from surrounding regions of the epitaxial layer;

doping said isolation island with impurities of said first type to form a base region;

forming a layer of polysilicon over said base region and doping it with impurities of said second type;

etching away portions of said polysilicon except for selected portions to form an emitter contact over said base region;

heating the structure to drive some of said second type impurities into said base region and reverse its doping so as to form an emitter region;

forming an insulating layer of a material upon which silicide will not form to insulate the sides but not the top of said emitter contact;

forming over said base region and emitter contact a layer of metal;

heat treating the structure to form silicide which covers and is self aligned with the top of said emitter contact and which covers the top of the base region and is self aligned with the perimeter of the isolation island;

forming a protective masking layer overlapping an edge of said silicide which is self aligned with the edge of said isolation island and which also protects a portion of the metal layer which is in electrical contact with said edge and which protects a portion of said metal layer outside perimeter of said isolation island which is in electrical contact with said silicide covering said base region;

etching away all the unprotected portions of said metal layer.

13. A process for making high performance bipolar and high performance MOS devices on the same die comprising the steps of:

forming a plurality of islands of silicon of a first conductivity type surrounded by an insulating material of a lower conductivity;

doping selected islands to a second conductivity type;

forming a layer of gate oxide over selected islands to contain MOS devices;

depositing polysilicon over all islands;

doping the polysilicon in selected regions with an impurity of a first conductivity type;

etching said polysilicon into predetermined electrode patterns;

doping the exposed portions of selected islands with an impurity of a type to form source and drain regions of said second conductivity type;

forming a layer of insulation material over the structure;

anisotropically etching said insulation material to form insulating spacers on predetermined surfaces of said polysilicon electrodes;

forming a layer of refractory metal over the structure;

heat treating to form silicide over all exposed silicon and polysilicon but not over insulation material;

masking selected areas of the refractory metal and silicide; and

etching off all refractory metal not masked.

14. The process of claim 13 wherein the step of forming a layer of insulation material includes the steps of thermally growing a layer of silicon dioxide and then depositing a layer of insulation material over said thermally grown layer.

15. The process of claim 13 wherein the step of heat treating to form silicide is comprised of a step of performing a heat pulse treatment of a duration only long enough to form said silicide.

16. The process of claim 13 wherein said step of masking selected areas of said refractory metal and silicide comprises the step of masking an area adjacent to and overlapping the source and drain regions of each MOS transistor and the base region of each bipolar transistor and extending out to a plurality of contact pad positions external to the island of each transistor such that, after etching, a conductive pattern of refractory metal will be left which is in electrical contact with the silicide formed on said source and drain regions and said base regions and which extends to a contact pad positions outside said islands where contacts to said sources and drains and bases may be made.