Method for making a self-aligned vertical thin-film transistor in a semiconductor device

• US 5,229,310 A
• Filed: 05/26/1992
• Issued: 07/20/1993
• Est. Priority Date: 05/03/1991
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Sivan, Richard D.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US07/887,956
• Time in Patent Office: 420 Days
• Field of Search: 437/41, 437/40, 437/56, 437/51, 437/59, 437/63, 437/913, 437/915, 357/42, 357/44, 148/DIG. 150
• US Class Current: 438/156
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/6675 Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS

Abstract

A thin-film transistor in a semiconductor device is self-aligned and vertically oriented. In one form of the present invention, the semiconductor device (10) has a vertical wall trench (18) formed in a first dielectric layer (16) and having a predetermined depth. A first current electrode (26) is formed on a bottom surface of the trench while a second current electrode (28) overlies the first dielectric material, each current electrode preferably being formed of polysilicon. A channel region (30) connecting the first and second current electrodes lies along the vertical wall of the trench and has a length substantially equal to the predetermined depth. A control electrode (36) is located within the trench and is also preferably formed of polysilicon. The control electrode is electrically isolated from the first current electrode and the channel region by a second dielectric layer (32).

Claims

1. A method for making a self-aligned vertical thin-film transistor in a semiconductor device comprising the steps of:

providing a substrate of a first dielectric material having an upper and lower surface, and a substantially vertical wall trench formed therein, the trench having a bottom surface which does not extend below the lower surface of the dielectric substrate and having a depth;

depositing a first conductive material overlying the dielectric substrate and substantially conforming to the trench;

forming a first current electrode in a portion of the first conductive material overlying the bottom surface of the trench;

forming a second current electrode in a portion of the first conductive material overlying the upper surface of the dielectric substrate;

forming a channel region in a portion of the first conductive material along the vertical wall of the trench between the first and second current electrodes;

forming a second dielectric material adjacent the channel region;

forming a control electrode of a second conductive material within the trench such that the control electrode substantially conforms to the wall of the trench, is electrically isolated from the channel region by the second dielectric material, and is electrically isolated from the first current electrode;

forming a third dielectric material adjacent the control electrode and within the trench;

forming a contact opening in the third dielectric material within the trench to expose a portion of the first current electrode; and

forming a contact to the exposed portion of the first current electrode, the contact being electrically coupled to the first current electrode and electrically isolated from the control electrode.

2. The method of claim 1 wherein the step of forming a channel region comprises forming a channel region having a length substantially equal to the depth of the trench.

3. The method of claim 1 wherein the step of depositing a first conductive material comprises depositing either amorphous silicon or polysilicon.

4. The method of claim 1 wherein the steps of forming a first current electrode, forming a second current electrode, and forming a channel region comprise the step of doping the first conductive material of the semiconductor device by ion implantation to form the first and second current electrodes and the channel region.

5. The method of claim 4 wherein the step of doping the first conductive material comprises doping the semiconductor device at an angle normal to the semiconductor device to prevent the channel region from being doped.

6. The method of claim 4 further comprising the step of forming a sacrificial sidewall spacer along the substantially vertical wall trench to prevent the channel region from being doped.

7. The method of claim 2 wherein the step of providing a substrate comprises providing a substrate having a substantially vertical wall trench having a depth of between approximately 0.5-2.0 μ

m.

8. The method of claim 1 wherein the step of providing a first dielectric material comprises providing a dielectric material selected from a group consisting of:

quartz, glass, and deposited SiO₂.

15. The method of claim 1 wherein the step of forming a contact comprises forming a contact which is encircled by the control electrode within the trench.

9. A method for making a self aligned vertical thin-film transistor in a semiconductor device comprising the steps of:

providing a substrate;

forming a first dielectric material overlying the substrate;

forming a second dielectric material on the first dielectric material, the second dielectric material having the ability to be etched selectively to the first dielectric material;

forming a trench in the second dielectric material using the first dielectric material as an etch stop which forms a bottom surface of the trench, the trench having substantially vertical sidewalls;

depositing a first conductive layer overlying the second dielectric material, the first conductive layer conforming to the trench;

doping the first conductive layer to form a first current electrode at the bottom of the trench, a second current electrode overlying the second dielectric material and adjacent the trench, and a channel region adjacent the second dielectric material along the trench sidewalls;

forming a third dielectric material adjacent the channel region;

forming a control electrode within and conforming to the trench and electrically isolated from the channel region and from the first current electrode by the third dielectric material;

forming a fourth dielectric material adjacent the control electrode and within the trench;

forming a contact opening in the fourth dielectric within the trench to expose a portion of the first current electrode; and

forming a contact in the contract opening which is electrically coupled to the first current electrode and electrically isolated from the control electrode.

10. The method of claim 9 wherein the step of depositing a first conductive layer comprises depositing either polysilicon or amorphous silicon.

11. The method of claim 9 wherein the step of doping the first conductive layer comprises implanting dopants into portions of the first conductive layer other than the channel region.

12. The method of claim 9 wherein the step of providing a substrate comprises providing a semiconductor substrate.

16. The method of claim 9 wherein the step of forming a contact comprises forming a contact which is encircled by the control electrode within the trench.

13. A method for making a self-aligned vertical thin-film transistor in a semiconductor device comprising the steps of:

providing a substrate having an overlying etch stop layer formed of a non-conductive material;

depositing a first dielectric material on the etch stop layer;

etching the first dielectric material to form a trench, wherein etching is terminated upon exposing, but substantially unaltering, a portion of the etch stop layer, the exposed portion of the etch stop layer forming a bottom surface of the trench;

depositing a conductive layer overlying the first dielectric material and conforming to the trench;

forming a first current electrode in a portion of the conductive layer overlying the bottom of the trench;

forming a second current electrode in a portion of the conductive layer overlying the first dielectric and adjacent the trench;

forming a channel region in a portion of the conductive layer between the first and second current electrodes;

forming a second dielectric material on the channel region of the conductive layer;

forming a control electrode within the trench and electrically isolated from the channel region by the second dielectric material;

patterning the control electrode and the second dielectric material to expose a portion of the first current electrode within the trench; and

forming a contact to the exposed portion of the first current electrode.

14. The method of claim 13 wherein the steps of forming a first current electrode, forming a second current electrode, and forming a channel region comprise doping selected portions of the conductive layer using ion implantation.

17. The method of claim 13 wherein the step of forming a contact comprises forming a contact which is encircled by the control electrode within the trench.