High voltage lateral enhancement IGFET

• US 5,229,633 A
• Filed: 01/17/1992
• Issued: 07/20/1993
• Est. Priority Date: 06/08/1987
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Bird, Philip H., Fisher, Carole A., Paxman, David H.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/822,492
• Time in Patent Office: 550 Days
• Field of Search: 357/23.8, 357/23.12, 357/23.13, 257/339, 257/343, 257/409, 257/603
• US Class Current: 257/339
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 21/8236 Combination of enhancement and depletion transistors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7821 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7823 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Abstract

A method of manufacturing a semiconductor device including both an enhancement (1) insulated gate field effect transistor (IGFET) and a depletion (2) mode IGFET is described. Impurities are introduced into a first region or epitaxial layer (4) of one conductivity type adjacent a given surface (3a) of a semiconductor body (3) to provide, for both the enhancement mode (1) and for the depletion mode (2) IGFET, a second region (5) of the opposite conductivity type adjacent the given surface, a source region (9) of a first conductivity type adjacent the given surface (3a) and surrounded by the second region (5) and a drain region (10) of the first conductivity type having a relatively lightly doped drain extension region (11) adjacent the given surface and extending toward the source region (9). First and second insulated gates (12) are provided on first and second areas (31a) and (31b), respectively, of the given surface to provide a respective gate connection between each source region and the associated drain region (10). The relative doses of impurities introduced to provide the second regions (5) and the relatively lightly doped drain extensions (11) received by the first area (31a) and the second area (31b) are independently controlled so as to provide adjacent the first area (31a) a channel area (13) of a second conductivity type and adjacent the second area (31b) a channel area (13'"'"') of the first conductivity type.

Claims

1. A lateral insulated gate field effect transistor comprising

(a) a first region of one conductivity type adjacent to a surface of a semiconductor body;

(b) a second region of an opposite conductivity type adjacent to said surface, said second region including

(i) a first subsidiary region, and

(ii) a relatively lightly doped further subsidiary region extending away from said first subsidiary region;

(c) a source region of said one conductivity type adjacent to said surface, said first subsidiary region surrounding said source region;

(d) a drain region of said one conductivity type adjacent to said surface, said drain region being spaced apart from said source region, said further subsidiary region surrounding said drain region;

(e) a relatively lightly doped drain extension region adjacent to said surface, said relatively lightly doped drain extension region extending within said further subsidiary region toward said source region; and

(f) an insulated gate overlying a channel area of said first subsidiary region, said insulated gate providing a gate connection between said source region and said drain region.

2. A transistor according to claim 1, wherein said first subsidiary region, said source region, and said drain region are self-aligned to said insulated gate.

3. A transistor according to claim 2, wherein another region of said one conductivity type is disposed within said second region adjacent to said surface, said another region being separated from said source region, wherein said source region is shorted to said second region, and wherein an electrical connection is disposed between said insulated gate and said another region, said electrical connection providing a zener diode between said insulated gate and said second region.

4. A transistor according to claim 1, wherein another region of said one conductivity type is disposed within said second region adjacent to said surface, said another region being separated from said source region, wherein said source region is shorted to said second region, and wherein an electrical connection is disposed between said insulated gate and said another region, said electrical connection providing a zener diode between said insulated gate and said second region.