High density data storage using stacked wafers

• US 5,229,647 A
• Filed: 09/21/1992
• Issued: 07/20/1993
• Est. Priority Date: 03/27/1991
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gnadinger, Alfred P.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Crane, Sara W.
• Application Number:
  US07/947,942
• Time in Patent Office: 302 Days
• Field of Search: 257/621, 257/686, 257/738, 257/748, 257/774, 257/777, 257/785
• US Class Current: 257/785
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/72 Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A solid-state memory unit is constructed using stacked wafers containing a large number of memory units in each wafer. Vertical connections between wafers are created using bumps at the contact points and metal in through-holes aligned with the bumps. The bumps on one wafer make contact with metal pads on a mating wafer. Mechanical bonding between the bumps and mating metal pads on another wafer is preferably avoided so that fractures due to thermal expansion differentials will be prevented. Serial addressing and data access is employed for the memory units to minimize the number of connections needed. Also, the metal pads, through-holes and bumps are formed at corners of the die and thus shared with adjacent units whenever possible, further reducing the number of vertical connections.

Claims

1. A stacked wafer device comprising:

(a) a plurality of semiconductor wafers arranged in a stack;

(b) each wafer having a plurality of connection pads formed on the upper face of the wafer, the connection pads made of a first metallic material;

(c) each wafer further having a plurality through-holes axially aligned with the connection pads, each through-hole extending through the wafer to an opposite face of the wafer;

(d) each wafer further including a plurality of solid bumps of a second metallic material, each bump engaging and making electrical contact with a connection pad formed on the wafer at an interface and extending through the through-hole of another wafer to make electrical contact with a connection pad formed on the other wafer;

(e) the first and second metallic materials selected such that the metallic materials do not form a rigid mechanical bond at the interface between the connection pad and the bump.

2. The device of claim 1 wherein the first metallic material comprises aluminum and the second metallic material comprises a malleable metal.

3. The device of claim 2 wherein the second metallic material comprises gold.

4. The device of claim 1 further including means for applying a mechanical force to the stack of wafers in a direction substantially perpendicular to the interface between the connection pad and the bump.

5. The device of claim 4 wherein the means for applying a mechanical force comprises a spring.

6. The memory device of claim 1 wherein each solid bump makes electrical contact to an interior semiconductor region beneath one of said connection pads.

7. A stacked wafer memory device comprising:

(a) a stack of semiconductor wafers, each wafer including a plurality of memory unit pairs arranged in a regular pattern, the memory unit pairs having a generally rectangular configuration;

(b) each of the memory unit pairs having four power supply connection areas, one positioned at each corner of the rectangle;

two clock connection areas positioned on first opposing sides of the rectangle;

two ground connection areas positioned on second opposing sides of the rectangle; and

a combined address and input and output connection area, positioned substantially in the center of the rectangle;

(c) each wafer having a plurality of connection pads formed on the upper face of the wafer at positions defined by the connection areas, the connection pads comprising a first metallic material;

(d) each wafer further having a plurality through-holes axially aligned with the connection pads, each through-hole extending through the wafer to an opposite face of the wafer;

(e) each wafer further including a plurality of solid bumps of a second metallic material, each bump engaging and making electrical contact with a connection pad formed on the wafer at an interface and extending through the through-hole of another wafer to make electrical contact with a connection pad formed on the other wafer;

(f) the first and second metallic materials selected such that the metallic materials do not form a rigid mechanical bond at the interface between the connection pad and the bump.

8. The memory device of claim 7 wherein the first metallic material comprises aluminum and the second metallic material comprises a malleable metal.

9. The memory device of claim 8 wherein the second metallic material comprises gold.

10. The memory device of claim 7 wherein each bump is isolated from the other wafer by an insulator coating on the sidewalls of a through-hole.

11. The memory device of claim 7 wherein each solid bump makes electrical contact to an interior semiconductor region beneath one of said connection pads.

12. The memory device of claim 7 wherein each power supply and clock connection area is shared by four memory units and each ground and combined address and input and output connection area is shared by two memory units.

13. A stacked wafer memory device comprising:

(a) a stack of semiconductor wafers, each wafer including a plurality of memory unit pairs arranged in a regular pattern, the memory unit pairs having a generally rectangular configuration;

(b) each of the memory unit pairs having four power supply connection areas, one positioned at each corner of the rectangle;

two clock connection areas positioned on first opposing sides of the rectangle;

two ground connection areas positioned on second opposing sides of the rectangle; and

a combined address and input and output connection areas, positioned substantially in the center of the rectangle;

(c) each wafer having a plurality of connection pads formed on the upper face of the wafers at positions defined by the connection areas, the connection pads comprising aluminum;

(d) each wafer further having a plurality through-holes axially aligned with the connection pads, each through-hole extending through the wafer to an opposite face of the wafer;

(e) each wafer further including a plurality of solid bumps comprising gold, each bump engaging and making electrical contact with a connection pad formed on the wafer at an interface and extending through the through-hole of another wafer to make electrical contact with a connection pad formed on the other wafer;

the bump isolated from the other wafer by an insulator coating on the sidewalls of the through-hole;

(f) wherein the aluminum pad and the gold bump do not form a rigid mechanical bond at the interface between the connection pad and the bump; and

(g) means for applying a mechanical force to the stack of wafers in a direction substantially perpendicular to the interface between the connection pad and the bump.

14. The memory device of claim 13 wherein each solid bump makes electrical contact to an interior semiconductor region beneath one of said connection pads.