Low power complementary MOSFET digital signal buffer circuit

• US 5,229,659 A
• Filed: 10/16/1991
• Issued: 07/20/1993
• Est. Priority Date: 10/16/1991
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Sandhu, Bal S.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): Sanders, Andrew
• Application Number:
  US07/777,586
• Time in Patent Office: 643 Days
• Field of Search: 307/448, 307/451, 307/296.5, 307/475
• US Class Current: 326/83
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A low power complementary MOSFET buffer circuit includes an input complementary MOSFET inverter with a plurality of serially coupled diode-connected complementary MOSFETs and an output complementary MOSFET inverter. An input digital signal drives one of the input inverter'"'"'s MOSFET gates, and passes through the diode-connected MOSFETs to be biased, or level-shifted, prior to driving the input inverter'"'"'s other MOSFET gate. Driving the input inverter'"'"'s MOSFET gates with both the input digital signal directly and its biased equivalent ensures that, when each of the input inverter'"'"'s MOSFETs is turned "off" in accordance with the logic level of the input digital signal, it is turned off more fully, thereby minimizing power dissipation. The inverted digital signal outputted from the input inverter drives both of the output inverter'"'"'s MOSFET gates. The original input digital signal also drives one of the output inverter'"'"'s MOSFET sources, whereby the low-to-high transition time of the output digital signal is reduced.

Claims

1. An improved complementary MOSFET buffer circuit including a first complementary MOSFET inverter comprising first and second complementary MOSFETs with, respectively, first and second MOSFET sources, mutually coupled first and second MOSFET gates for receiving a first digital signal, and mutually coupled first and second MOSFET drains for providing an output digital signal, wherein the improvement comprises:

a second complementary MOSFET inverter comprising third and fourth complementary MOSFETs which are mutually coupled in a totem-pole topology and have, respectively, third and fourth MOSFET gates for receiving an input digital signal and a second digital signal, respectively, and mutually coupled third and fourth MOSFET drains coupled to said mutually coupled first and second MOSFET gates; and

a plurality of diode-connected MOSFETs coupled serially between said third and fourth MOSFET gates for receiving said input digital signal and providing said second digital signal to said fourth MOSFET gate.

2. An improved complementary MOSFET buffer circuit as recited in claim 1, wherein said improvement further comprises coupling means for coupling said third MOSFET gate to said first MOSFET source.

3. A complementary MOSFET buffer circuit for receiving and buffering a digital signal, said complementary MOSFET buffer circuit comprising:

first complementary MOSFET inverter means for receiving an input digital signal and a biased input digital signal, and for providing a first inverted digital signal; and

signal biasing means for receiving said input digital signal via a MOSFET channel and providing said biased input digital signal.

4. A complementary MOSFET buffer circuit as recited in claim 3, wherein said first complementary MOSFET inverter means comprises first and second complementary MOSFETs which are mutually coupled in a totem-pole topology and have, respectively, first and second MOSFET gates for receiving said input digital signal and said biased input digital signal, respectively, and mutually coupled first and second MOSFET drains for providing said first inverted digital signal.

5. A complementary MOSFET buffer circuit as recited in claim 3, wherein said signal biasing means comprises a plurality of diode-connected MOSFETs.

6. A complementary MOSFET buffer circuit as recited in claim 3, further comprising second complementary MOSFET inverter means for receiving said first inverted digital signal and for providing a second inverted digital signal.

7. A complementary MOSFET buffer circuit as recited in claim 6, wherein said second complementary MOSFET inverter means comprises third and fourth complementary MOSFETs which are mutually coupled in a totem-pole topology and have, respectively, mutually coupled third and fourth MOSFET gates for receiving said first inverted digital signal, and mutually coupled third and fourth MOSFET drains for providing said second inverted digital signal.

8. A complementary MOSFET buffer circuit for receiving and buffering a digital signal, said complementary MOSFET buffer circuit comprising:

input-biased complementary MOSFET input inverter means for receiving and biasing an input digital signal, and for providing a first inverted digital signal, wherein said input digital signal is received via a MOSFET channel and a MOSFET gate; and

input-coupled complementary MOSFET output inverter means for receiving said first inverted digital signal and said input digital signal, and for providing a second inverted digital signal.

9. A complementary MOSFET buffer circuit as recited in claim 8, wherein said input-coupled complementary MOSFET output inverter means comprises third and fourth complementary MOSFETs which are mutually coupled in a totem-pole topology and have, respectively, mutually coupled third and fourth MOSFET gates for receiving said first inverted digital signal, a third MOSFET source for receiving said input digital signal and a fourth MOSFET source, and third and fourth mutually coupled MOSFET drains for providing said second inverted digital signal.

10. A digital signal buffering method for receiving and buffering a digital signal, comprising the steps of:

receiving an input digital signal via a MOSFET channel;

biasing said received input digital signal to provide a biased input digital signal; and

inputting said input digital signal and said biased input digital signal to a first complementary MOSFET inverter to provide a first inverted digital signal.

11. A digital signal buffering method as recited in claim 10, wherein said step of biasing said received input digital signal to provide a biased input digital signal comprises inputting said received input digital signal to a plurality of diode-connected MOSFETs and outputting therefrom said biased input digital signal.

12. A digital signal buffering method as recited in claim 10, wherein said step of inputting said input digital signal and said biased input digital signal to a first complementary MOSFET inverter to provide a first inverted digital signal comprises:

inputting said input digital signal to a first MOSFET gate;

inputting said biased input digital signal to a second MOSFET gate; and

outputting said first inverted digital signal from mutually coupled first and second MOSFET drains.

13. A complementary MOSFET buffer circuit for receiving and buffering a digital signal, said complementary MOSFET buffer circuit comprising:

first complementary MOSFET inverter means for receiving an input digital signal and a biased input digital signal, and for providing a first inverted digital signal;

signal biasing means for receiving said input digital signal and providing said biased input digital signal; and

second complementary MOSFET inverter means for receiving said input digital signal and said first inverted digital signal, and for providing a second inverted digital signal.

14. A complementary MOSFET buffer circuit as recited in claim 13, wherein said second complementary MOSFET inverter means comprises third and fourth complementary MOSFETs which are mutually coupled in a totem-pole topology and have, respectively, a third MOSFET source for receiving said input digital signal and a fourth MOSFET source, third and fourth mutually coupled MOSFET gates for receiving said first inverted digital signal, and third and fourth mutually coupled MOSFET drains for providing said second inverted digital signal.

15. A complementary MOSFET buffer circuit for receiving and buffering a digital signal, said complementary MOSFET buffer circuit comprising:

input-biased complementary MOSFET input inverter means for receiving and biasing an input digital signal, and for providing a first inverted digital signal, wherein said input-biased complementary MOSFET input inverter means includes a plurality of diode-connected MOSFETs, and first and second complementary MOSFETs which are mutually coupled in a totem-pole topology and have, respectively, a first MOSFET gate for receiving said input digital signal and a second MOSFET gate, first and second MOSFET sources, and mutually coupled first and second MOSFET drains for providing said first inverted digital signal, and wherein said plurality of diode-connected MOSFETs is coupled to said first and second MOSFET gates; and

input-coupled complementary MOSFET output inverter means for receiving said first inverted digital signal and said input digital signal, and for providing a second inverted digital signal.

16. A digital signal buffering method for receiving and buffering a digital signal, comprising the steps of:

receiving an input digital signal;

biasing said input digital signal to provide a biased input digital signal;

inputting said input digital signal and said biased input digital signal to a first complementary MOSFET inverter to provide a first inverted digital signal; and

inputting said input digital signal and said first inverted digital signal to a second complementary MOSFET inverter to provide a second inverted digital signal.

17. A digital signal buffering method as recited in claim 16, wherein said step of inputting said input digital signal and said first inverted digital signal to a second complementary MOSFET inverter to provide a second inverted digital signal comprises:

inputting said input digital signal to a MOSFET source;

inputting said first inverted digital signal to mutually coupled third and fourth MOSFET gates; and

outputting said second inverted digital signal from mutually coupled third and fourth MOSFET drains.