Built-in self-test (BIST) circuit

• US 5,230,000 A
• Filed: 04/25/1991
• Issued: 07/20/1993
• Est. Priority Date: 04/25/1991
• Status: Expired due to Term

• Current Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Original Assignee: AT&T, Inc.
• Inventors: Stroud, Charles E., Mozingo, Kenneth D.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Chung, Phung M.
• Application Number:
  US07/693,114
• Time in Patent Office: 817 Days
• Field of Search: 371/22.4, 371/22.5, 371/20.5, 371/22.1, 371/22.6, 371/25.1, 371/61, 371/62, 370/112
• US Class Current: 714/732
• CPC Class Codes: G01R 31/31716 Testing of input or output with loop-back
• CPC Class Codes: G01R 31/3185 Reconfiguring for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 2201/83 the solution involving signatures

Abstract

Testing of data path circuitry (12) within an integrated circuit chip (10) is accomplished by a test circuit (22) comprised of a Signature Analysis Register (SAR) (30). The SAR (30) generates test signals for input to data path circuitry (12) and compacts response signals produced by the data path circuitry following receipt of the test signals. A blocking circuit (28) blocks an initial one of the response signals from being received by the SAR (30) until the test signals from the SAR have propagated through the data path circuitry (12). Bypass multiplexers (34) multiplex the test signals generated by the SAR (30) with input data normally supplied to the data path circuitry (12) to allow the test circuit (22) to be bypassed during intervals other than testing. Loopback multiplexers (26) are also provided to multiplex the output data of the data path circuitry (12) with the input data received by the data path circuitry (12) to allow for testing of a chain of integrated circuits (10 ) on a circuit board (53).

Claims

1. A method for testing an electronic circuit which is normally supplied with input data, comprising the steps of:

(a) multiplexing input data which is normally supplied to an electronic circuit with at least one test signal from a signature analysis register so that during a preselected interval, the test signal is applied to the electronic circuit to cause it to generate a response signal of a known state when the electronic circuit is operating properly, while during intervals other than the preselected interval, the input data is supplied to the electronic circuit;

(b) supplying each response signal, through a delay circuit, to the signature analysis register;

(c) delaying, at the delay circuit, an initial response signal prior to passage to the signature analysis register;

(d) compacting, at the signature analysis register, each successive response signal with the response signals previously applied to the signature analysis register to yield a signature representative of the state of the compacted signals;

(e) repeating the steps of (a), (b) and (d) for a prescribed number of times; and

(f) comparing the signature of the compacted response signals to a signature which represent a fault-free condition to detect if any faults are present.

2. The method according to claim 1 further including the step of multiplexing the response signals applied to the signature analysis register with the input data supplied to the electronic circuit.

3. The method according to claim 1 wherein the initial response signal is applied to the signature analysis register only after an interval at least as long as that required for the test signal to propagate through the electronic circuit being tested.

4. The method according to claim 1 further including the step of seeding the signature analysis register with an initial value prior to testing of the electronic circuit.

5. A method for testing a circuit board carrying a plurality of individual electronic circuits connected so that a first one of the circuits drives each of the others, comprising the steps of:

(a) multiplexing input data which is normally supplied to a first electronic circuit on a circuit board, which drives each of a plurality of second electronic circuits on the board, with at least one test signal from a signature analysis register, so that during a preselected interval, the test signal is applied to the first electronic circuit which generates a response signal for propagation through to each of the second electronic circuits driven thereby, while during intervals other than the preselected interval, the input data is supplied to said first electronic circuit;

(b) supplying the response signal from a last one of said second electronic circuits, through a delay circuit, to the signature analysis register;

(c) delaying, at the delay, circuit an initial response signal prior to passage to the signature analysis register;

(d) compacting, at the signature analysis register, each successive response signal with the response signals previously applied to the signature analysis register to yield a signature representative of the state of the compacted signals;

(e) repeating the steps of (a), (b) and (d) for a prescribed number of times; and

(f) comparing the signature of the compacted response signals to a signature obtained for a fault-free circuit board to detect if any faults are present.

6. The method according to claim 5 wherein the initial response signal is applied to the signature analysis register for compaction after an interval at least as long as that required for the test signal to propagate through to the last one of the second electronic circuits.

7. The method according to claim 5 further including the step of seeding the signature analysis register with an initial value prior to testing.

8. A built-in self-test circuit for insertion within an electronic device for testing the device, comprising:

a signature analysis register for generating test signals for input to an electronic device to cause the device to generate response signals, and for compacting such response signals to yield a signature indicative of the operation of the device;

bypass multiplexer means coupled between the electronic device and the signature analysis register for multiplexing input data normally supplied to the electronic device with test signals from the signature analysis register, so that during preselected intervals, the test signals from the signature analysis register feed the electronic device, while during intervals other than said preselected intervals, said input data is fed to the electronic device;

loopback multiplexing means for multiplexing the input data normally supplied to the electronic device with response signals produced by the electronic device, so that during selected intervals, the loopback multiplexing means passes the response signals, while during other than said selected intervals, the loopback multiplexing means passes the input data;

blocking means coupled between the loopback multiplexing means and the signature analysis register for delaying transmission of an initial one of the response signals from reaching the signature analysis register for a predetermined interval; and

controller means for controlling the signature analysis register, loopback multiplexing means, bypass multiplexing means, and the blocking means.

9. The apparatus according to claim 8 wherein the controller means comprises a counter.

10. The apparatus according to claim 8 wherein the electronic device has n separate data inputs and wherein the signature analysis register comprises n channels, each channel comprised of:

a multiplexer having a first input and a second input;

a flip-flop for producing an output signal in accordance with a signal provided by the multiplexer, the flip-flop output signal supplied to a first input of the multiplexer; and

an exclusive OR gate having its output coupled to a second input of the multiplexers, the exclusive OR gate having a first input coupled to a separate one of the n data inputs to the electronic device and a second input coupled to the output of the flip-flop associated with the n-1 channel.

11. The apparatus according to claim 10 wherein the loopback multiplexing means comprises:

n separate multiplexers, each having a first input coupled to a separate one of the n data inputs to the data path circuitry and a second input supplied with an output of the electronic device.

12. The apparatus according to claim 11 wherein the blocking means comprises:

n separate AND gates, each supplied at a first input with the output of a separate one of the n loopback multiplexers and a second input supplied with a control signal from the controller means.