Offset frequency converter for phase/amplitude data measurement receivers

• US 5,230,097 A
• Filed: 03/09/1990
• Issued: 07/20/1993
• Est. Priority Date: 03/09/1990
• Status: Expired due to Fees

• Current Assignee: Scientific-Atlanta Incorporated (Cisco Systems, Inc.)
• Original Assignee: Scientific-Atlanta Incorporated (Cisco Systems, Inc.)
• Inventors: Currie, Charles H., Caldwell, Owen M.
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): Faile, Andrew
• Application Number:
  US07/491,161
• Time in Patent Office: 1,229 Days
• Field of Search: 455/264-265, 455/259, 455/318-319, 455/316, 455/323, 455/324, 455/208-209, 455/314-315, 331/2, 331/25
• US Class Current: 455/226.1
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/0007 wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
• CPC Class Codes: H04B 1/26 for superheterodyne receivers multiple frequency-changing H03D7/16

Abstract

An offset frequency converter for the intermediate frequency (IF) stages of a multi-channel radio frequency (RF) phase/amplitude measurement receiver, particularly useful for measuring the performance characteristics of antennas. The converter allows use of noncoherent transmitter and receiver local oscillator sources which utilize digital frequency synthesizers and enables harmonic mixing to be employed when the tuning resolution of the receiver local oscillator is incremental. The converter samples an incoming first intermediate frequency signal IF₁ in a reference channel, which typically is obtained by mixing an LO source in the receiver with an incoming signal from a reference antenna. The IF₁ sample is then upconverted with an upconversion signal to a higher frequency, filtered, and the downconverted with a downconversion signal to an IF₁ +IF₂ signal offset from the IF₁ sample by a lower second intermediate frequency IF₂. The added frequency offset IF₂ is derived from a time stabilized source independent of the transmitter but coherent with the receiver LO. The mixed IF₁ +IF₂ signal is heterodyned with signals in both the signal channel from the antenna under test and the reference channel to obtain coherent outputs at IF₂ which differ by phase and magnitude corresponding to the characteristics of the antenna under test. The circuit exhibits high frequency agility and obviates the need for coherency between the receiver LO and transmitter LO.

Claims

1. In or for a radio frequency apparatus, an intermediate frequency (IF) circuit for providing an IF output signal derived from a higher frequency input signal originating from a remote frequency source at a frequency coherent with a reference signal generated within said radio frequency apparatus, comprising:

a local oscillator including a programmably variable digital frequency synthesizer, said local oscillator being independent of said remote frequency source, said local oscillator providing said reference signal;

offset frequency converter means responsive to frequency differences within a predetermined range of frequencies between said reference signal and said input signal, for providing a stable mixing signal; and

utilization means responsive to said input signal and said mixing signal to provide said IF output signal.

2. The IF circuit of claim 1, wherein said offset frequency converter is responsive to said input signal and a stable clock reference signal to provide said mixing signal which when supplied as a local oscillator frequency source to second converters in said IF circuit results in said IF output signal being coherent with said stable clock reference.

3. The IF circuit of claim 2, wherein said offset frequency converter comprises:

an oscillator circuit for providing an upconversion LO signal and a downconversion LO signal,

said downconversion LO signal being different in frequency from said upconversion LO signal by said clock reference signal; and

a frequency converter stage responsive to said upconversion LO signal, said downconversion LO signal, and said input signal to provide said IF output signal.

4. The IF circuit of claim 3, wherein said upconversion LO signal and said downconversion LO signals are higher in frequency than said input signal.

5. The IF circuit of claim 3, wherein said oscillator circuit comprises:

a fixed oscillator operative at said upconversion LO signal frequency;

a voltage-controlled oscillator responsive to a control voltage;

means responsive to said upconversion signal and said downconversion signal for obtaining a difference signal;

a phase locked loop operative to lock said difference signal to said clock reference signal and provide said control voltage,

whereby said voltage-controlled oscillator provides said downconversion LO signal at the frequency of said upconversion signal plus said clock reference signal.

6. The IF circuit of claim 3, wherein said frequency converter stage comprises:

a frequency upconverter responsive to said input signal and said upconversion LO signal to provide a second upconverted IF signal (IF₃);

filter means for removing unwanted frequencies from said upconverted IF signal (IF₃); and

a second frequency converter responsive to said upconverted IF signal (IF₃) and said downconversion LO signal to provide said output signal (IF₁ +IF₂).

7. The IF circuit of claim 6, wherein said upconverted IF signal (IF₃) is higher in frequency than the frequency of said input signal but lower than said upconversion LO signal.

8. The IF circuit of claim 6, wherein said upconversion signal is 120.0 MHz, wherein said upconverted IF signal (IF₃) is 75.0 MHz, and said input signal is nominally 45.0 MHz.

9. The IF circuit of claim 6, wherein said upconverted signal (IF₃) comprises a signal lower in frequency than the second harmonic of said input signal.

10. The IF circuit of claim 6, further comprising bandpass filter means subsequent to said second frequency converter for filtering unwanted frequencies resulting from the mixing process.

11. The IF circuit of claim 3, wherein said upconversion LO signal is lower by the frequency of said clock reference signal than said downconversion LO signal.

12. The IF circuit of claim 11, wherein said upconversion LO signal is 120.0 MHz and said clock reference signal is 100 kHz.

13. The IF circuit of claim 1, wherein said utilization means comprises an RF measurement receiver.

14. The IF circuit of claim 13, wherein said RF measurement receiver comprises a signal channel and a reference channel, and wherein said input signal is derived from said reference channel.

49. The IF circuit of claim 1, wherein said remote frequency source comprises a transmitting system including a second digital frequency synthesizer, and wherein said input signal comprises a signal derived from a test antenna operative for receiving signals transmitted from said transmitting system.

50. The IF circuit of claim 1, wherein said local oscillator provides a clock reference signal, and further comprising IF reference signal generating means responsive to said clock reference signal for providing said reference signal as an IF reference signal.

15. In or for a radio frequency receiver including a local oscillator stage having a frequency synthesizer for generating a local oscillator signal at steps of predetermined frequency increments and a harmonic mixer for mixing said local oscillator signal with an incoming RF signal from a remote frequency source independent of said local oscillator to obtain a downconverted intermediate frequency (IF) output signal, an improved high agility frequency converter, comprising:

means responsive to said local oscillator stage for mixing said local oscillator signal with said incoming signal to provide a first IF signal (IF₁)

means for sampling said IF₁ signal to provide a reference IF₁ signal;

means for providing a stable clock reference signal at a predetermined second IF frequency signal (IF₂);

offset frequency converter means responsive to said reference IF₁ signal and said second IF frequency signal for providing an IF₁ +IF₂ signal; and

means for mixing said IF₁ +IF₂ signal with said first IF signal (IF₁) to provide said IF output signal at said second IF frequency IF₂,

whereby said harmonic mixer may be utilized even when the receiver processes a signal from a transmitter which is non-coherent with respect to said local oscillator.

16. The frequency converter of claim 15, wherein said incoming signal is mixed with said local oscillator signal to provide a reference channel first IF signal (IF_1REF) and a signal channel first IF signal (IF_1SIG), and wherein said sampling means samples said reference channel first IF signal (IF_1REF).

17. The frequency converter of claim 15, wherein said incoming RF signal comprises a signal channel incoming RF signal derived from a test antenna and a reference channel incoming RF signal derived from a reference antenna, wherein said reference channel incoming RF signal is mixed with said local oscillator signal to provide a reference channel first IF signal (IF_1REF) and said signal channel incoming RF signal is mixed with said local oscillator signal to provide a signal channel first IF signal (IF_1SIG), and

wherein said mixed IF₁ +IF₂ signal is mixed with both said IF_1REF signal and said IF_1SIG signal to obtain separate IF output signals IF_2REF and IF_2SIG, both at said second IF frequency IF₂, such that IF_2REF and IF_2SIG are coherent in frequency but differ in phase and amplitude corresponding to differences in the signal channel incoming RF signal and reference channel incoming RF signal.

18. The frequency converter of claim 15, wherein said offset frequency converter comprises:

an oscillator circuit for providing an upconversion LO signal and a downconversion LO signal,

said downconversion LO signal being different in frequency from said upconversion LO signal by said clock reference signal; and

a frequency converter stage responsive to said first upconversion LO signal, said downconversion LO signal, and said clock reference signal to provide said IF₁ +IF₂ output signal.

19. The frequency converter of claim 18, wherein said oscillator circuit comprises:

a fixed oscillator operative at said upconversion LO frequency;

a voltage-controlled oscillator responsive to a control voltage;

means responsive to said upconversion LO signal and said downconversion LO signal for obtaining a difference signal;

a phase locked loop operative to compare said difference signal to said clock reference signal and provide said control voltage,

whereby said voltage-controlled oscillator provides said downconversion LO signal at the frequency of said upconversion LO signal plus said clock reference signal.

20. The frequency converter of claim 18, wherein said frequency converter stage comprises:

a frequency upconverter responsive to said reference IF₁ signal and said upconversion LO signal to provide an upconverted IF signal (IF₃);

filter means for removing unwanted frequencies resulting from the mixing process from said reference IF₁ signal; and

a frequency downconverter responsive to said upconverted IF signal (IF₃) and said downconversion LO signal to provide said IF₁ +IF₂ output signal.

21. The frequency converter of claim 20, wherein said upconverted IF signal (IF₃) is higher in frequency than the frequency of said reference IF₁ signal but lower than said upconversion LO signal.

22. The frequency converter of claim 20, wherein said upconversion signal is 120.0 MHz, wherein said upconverted IF signal (IF₃) is 75.0 MHz, and said reference IF₁ signal is 45.0 MHz.

23. The frequency converter of claim 20, wherein said upconverted IF signal (IF₃) comprises a signal lower in frequency than the second harmonic of said reference IF₁ signal.

24. The frequency converter of claim 18, wherein said upconversion LO signal is lower by the frequency of said clock reference signal than said downconversion LO signal.

25. The frequency converter of claim 24, wherein said upconversion LO signal is 120.0 MHz and said clock reference signal is 100 kHz.

26. An intermediate frequency (IF) stage of a radio frequency (RF) antenna measurement receiver, said receiver being operative for measuring the characteristics of a test antenna which receives a transmitted signal at a first frequency derived from a remote frequency source, comprising:

means for receiving a reference signal input from a reference antenna positioned to receive said transmitted signal;

means for receiving a test signal input from an antenna under test positioned to receive said transmitted signal;

a first reference channel IF means responsive to a receiver local oscillator signal derived from a receiver local oscillator independent of the remote frequency source, for downconverting said reference signal input into a first reference intermediate frequency (IF_1REF) signal;

a first test channel IF means responsive to said receiver local oscillator signal for downconverting said test signal input into a first signal intermediate frequency (IF_1SIG) signal;

sampling means for taking a sample of said IF_1REF signal to provide an IF_1REF sample signal;

means for generating a second intermediate frequency reference signal (REF IF₂);

offset frequency converter means responsive to said IF_1REF sample signal and said REF IF₂ signal to provide a mixed IF₁ +IF₂ signal;

means for splitting said IF₁ +IF₂ signal into two signal portions;

means for mixing one portion of said IF₁ +IF₂ signal with said IF_1REF signal to provide an intermediate frequency output signal associated with said reference signal input (IF_2REF); and

means for mixing the other portion of said mixed IF₁ +IF₂ signal with said IF_1SIG signal to provide an intermediate frequency output signal (IF_2SIG) associated with said test signal input,

whereby said IF_2REF signal and said IF_2SIG signal are coherent in frequency notwithstanding a frequency difference between the receiver local oscillator signal from the receiver local oscillator and the transmitted signal from the remote frequency source.

27. The IF stage of claim 26, wherein said first reference IF means and said first test IF means comprises:

a programmable local oscillator (LO) operative at discrete frequency intervals to provide a first LO signal;

a power splitter for dividing said first LO signal into a LO signal for said first reference IF means and a LO signal for said first test IF means;

a frequency mixer for mixing said first LO signal with said reference signal to obtain said first reference intermediate frequency (IF_1REF) signal; and

a frequency mixer for mixing said first LO signal with said test signal to obtain said first signal intermediate frequency (IF_1SIG) signal.

28. The IF stage of claim 26, wherein said second IF reference signal (REF IF₂) is derived from a source independent of said transmitted signal.

29. The IF stage of claim 28, wherein said independent source comprises a stable clock oscillator.

30. The IF stage of claim 26, wherein said offset frequency converter comprises:

an oscillator circuit for providing a upconversion LO signal and a downconversion LO signal,

said downconversion LO signal being different in frequency by said second IF reference signal (REF IF₂); and

a frequency converter stage responsive to said upconversion LO signal, said downconversion LO signal, and said IF_1REF sample signal to provide said IF₁ +IF₂ signal.

31. The IF stage of claim 30, wherein said oscillator circuit comprises:

a fixed oscillator operative at said upconversion LO signal frequency;

a voltage-controlled oscillator responsive to a control voltage;

a mixer operative to mix said upconversion LO signal and said downconversion LO signal to obtain a difference signal; and

a phase locked loop operative to lock said difference signal to said second IF reference signal (REF IF₂) and provide said control voltage,

whereby said voltage-controlled oscillator provides said downconversion LO signal at the frequency of said upconversion LO signal plus said second IF reference signal (REF IF₂).

32. The IF stage of claim 30, wherein said frequency converter stage comprises:

a frequency upconverter responsive to said IF_1REF sample signal and said upconversion LO signal to provide an upconverted IF signal (IF₃);

filter means for removing unwanted frequency components due to the mixing process from said upconverted IF signal (IF₃); and

a frequency downconverter responsive to said upconverted IF signal (IF₃) and said downconversion LO signal to provide said IF₁ +IF₂ output signal.

33. The IF stage of claim 32, wherein said upconverted IF signal (IF₃) is higher in frequency than the frequency of said IF_1REF sample signal but lower than said upconversion LO signal.

34. The IF stage of claim 33, wherein said upconversion LO signal is 120.0 MHz, wherein said upconverted IF signal (IF₃) is 75.0 MHz, and said IF_1REF sample signal is 45.0 MHz.

35. The IF stage of claim 32, wherein said upconverted IF signal (IF₃) comprises a signal lower in frequency than the second harmonic of said IF_1REF sample signal.

36. The IF stage of claim 32, further comprising bandpass filter means subsequent to said frequency downconverter for filtering unwanted frequency components due to the mixing process from said IF₁ +IF₂ output signal.

37. The IF stage of claim 30, wherein said upconversion LO signal is lower by the frequency of said second IF reference signal (REF IF₂) than said downconversion LO signal.

38. The IF stage of claim 37, wherein said upconversion LO signal is 120.0 MHz and said second IF reference signal (REF IF₂) is 100 kHz.

39. An offset frequency converter responsive to an input (IF_1REF) signal and a stable clock reference signal (REF IF₂) to provide an offset output (IF₁ +IF₂) signal which is the sum of said input signal and said clock reference signal, comprising:

means for providing a stable clock reference signal (REF IF₂);

an oscillator circuit for providing an upconversion LO signal and a downconversion LO signal,

said downconversion LO signal being different in frequency from said upconversion LO signal by said clock reference signal;

means in said oscillator circuit for controlling the difference between said upconversion LO signal and said downconversion LO signal to the frequency of said stable clock reference signal; and

a frequency converter stage responsive to said upconversion LO signal, said downconversion LO signal, and said input signal to provide said offset output signal.

40. The offset frequency converter of claim 39, wherein said upconversion LO signal and said downconversion LO signals are higher in frequency than said input signal.

41. The offset frequency converter of claim 39, wherein said oscillator circuit comprises:

an fixed oscillator operative at said upconversion LO signal frequency;

a voltage-controlled oscillator responsive to a control voltage;

a mixer operative to mix said upconversion LO signal and said downconversion LO signal to obtain a difference signal;

a phase locked loop operative to lock said difference signal to said clock reference signal and provide said control voltage,

whereby said voltage-controlled oscillator provides said downconversion LO signal at the frequency of said upconversion LO signal plus said clock reference signal.

42. The offset frequency converter of claim 39, wherein said frequency converter stage comprises:

a frequency upconverter responsive to said input signal and said upconversion LO signal to provide an upconverted IF signal (IF₃);

filter means for removing unwanted frequencies due to the mixing process for said upconverted IF signal (IF₃); and

a frequency downconverter responsive to said upconverted IF signal (IF₃) and said downconversion LO signal to provide said offset output signal.

43. The offset frequency converter of claim 42, wherein said upconverted IF signal (IF₃) is higher in frequency than the frequency of said input signal but lower than said upconversion LO signal.

44. The offset frequency converter of claim 43, wherein said upconversion LO signal is 120.0 MHz, wherein said upconverted IF signal (IF₃) is 75.0 MHz, and said input signal is nominally 45.0 MHz.

45. The offset frequency converter of claim 43, wherein said upconverted IF signal (IF₃) comprises a signal lower in frequency than the second harmonic of said input signal.

46. The offset frequency converter of claim 43, further comprising bandpass filter means subsequent to said frequency downconverter for filtering unwanted frequencies present in the mixing process from said offset output signal.

47. The offset frequency converter of claim 39, wherein said upconversion LO signal is lower by the frequency of said clock reference signal than said downconversion LO signal.

48. The offset frequency converter of claim 47, wherein said upconversion LO signal is 120.0 MHz and said clock reference signal is 100 kHz.

51. The offset frequency converter of claim 39, wherein said stable clock reference signal means comprises a local oscillator, and further comprising:

means for providing a first RF signal and a second RF signal both derived from a remote frequency source that is independent of said local oscillator; and

means for mixing said offset output signal with said first RF signal and said second RF signal,

whereby said first RF signal and said second RF signal are coherent in frequency relative to said local oscillator notwithstanding a frequency difference between said local oscillator and signals derived from said remote frequency source.

52. The offset frequency converter of claim 51, wherein said first RF signal is a signal channel signal in an antenna measurement receiver, and said second RF signal is a reference channel signal in said antenna measurement receiver.

53. The offset frequency converter of claim 39, wherein said difference controlling means comprises a phase locked loop for locking said downconversion LO signal to said stable clock reference signal.