Method of making a power VFET device using a p+ carbon doped gate layer

• US 5,231,037 A
• Filed: 04/30/1992
• Issued: 07/27/1993
• Est. Priority Date: 04/30/1992
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kim, Tae S., Morris, Francis J., Yuan, Han-Tzong
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US07/876,252
• Time in Patent Office: 453 Days
• Field of Search: 437/6, 437/24, 437/39, 437/40, 437/41, 437/176, 437/179, 437/184, 437/911, 437/959, 148/DIG. 40, 148/DIG. 56, 148/DIG. 140, 148/DIG. 126
• US Class Current: 438/193
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/66454 Static induction transistors [SIT], e.g. permeable base transistors [PBT]
• CPC Class Codes: H01L 29/66924 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: Y10S 148/04 Dopants, special

Abstract

This is a method of forming a vertical transistor device. The method comprises: forming a n-type source layer 12; forming a p+ carbon doped gate layer 14; forming a gate structure from the gate layer; and forming a n-type drain layer 16 over the gate structure to provide a buried carbon doped gate structure. The buried carbon doped gate structure provides a very small device with favorable on-resistance, junction capacitance, gate resistance, and gate driving voltage. Other devices and methods are also disclosed.

Claims

1. A method of forming a vertical transistor device comprising:

a. forming an n-type source layer;

b. forming a p+ carbon doped gate layer over said source layer;

c. forming a gate structure from said gate layer; and

d. forming a n-type drain layer over said gate structure.

2. The method of claim 1, wherein said source layer is formed on a substrate.

3. The method of claim 2, wherein said substrate has n+ doping.

4. The method of claim 1, wherein a cap layer is formed over said drain layer.

5. The method of claim 4, wherein said cap layer has n+ doping.

6. The method of claim 1, wherein said source layer, said gate layer, and said drain layer are GaAs.

7. The method of claim 1, wherein said source layer, said gate layer, and said drain layer are epitaxially formed.

8. The method of claim 1, wherein said gate structure is formed by an ECR etch.

9. A method of forming a vertical transistor device comprising:

a. forming an n-type source layer over a n+ substrate;

b. forming a p+ carbon doped gate layer over said source layer;

c. forming a gate structure from said gate layer;

d. forming a n-type drain layer over said gate structure;

e. forming a n+ cap layer over said drain layer;

f. implanting a p+ dopant to contact said gate structure;

g. forming a p-ohmic contact to said gate structure;

h. forming an n-ohmic source contact; and

i. forming an n-ohmic drain contact.

10. The method of claim 9, wherein said implanted p+ dopant is Be.

11. The method of claim 9, wherein said implanted p+ dopant is Zn.

12. The method of claim 9, wherein said p-ohmic contact is AuZn.

13. The method of claim 9, wherein said n-ohmic contact is PdGeIn.

14. The method of claim 9, wherein said drain layer, said gate layer, and said source layer are GaAs.