Process for thin film interconnect

• US 5,231,751 A
• Filed: 10/29/1991
• Issued: 08/03/1993
• Est. Priority Date: 10/29/1991
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: McGuire, Kathleen M., Sorce, Peter J., Kellner, Benedikt M. J., Sachdev, Krishna G.
• Primary Examiner(s): Arbes, Carl J.
• Application Number:
  US07/784,281
• Time in Patent Office: 644 Days
• Field of Search: 29/852, 156/901, 156/843, 156/652, 427/97, 437/203
• US Class Current: 29/852
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 2201/0154 Polyimide
• CPC Class Codes: H05K 2201/068 wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 2201/09554 Via connected to metal substrate
• CPC Class Codes: H05K 2201/09563 Metal filled via
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2203/0152 Temporary metallic carrier, e.g. for transferring material
• CPC Class Codes: H05K 3/0032 of organic insulating material
• CPC Class Codes: H05K 3/0035 of blind holes, i.e. having a metal layer at the bottom
• CPC Class Codes: H05K 3/0061 onto a metallic substrate, e.g. a heat sink heat sinks for electric apparatus H05K7/20
• CPC Class Codes: H05K 3/007 Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier H05K1/187, H05K3/20 and H05K3/4682 take precedence
• CPC Class Codes: H05K 3/388 by the use of a metallic or inorganic thin film adhesion layer
• CPC Class Codes: H05K 3/4076 by thin-film techniques
• CPC Class Codes: H05K 3/423 characterised by electroplating method
• CPC Class Codes: H05K 3/445 having insulated holes or insulated via connections through the metal core
• CPC Class Codes: H05K 3/4614 the electrical connections between the circuit boards being made during lamination
• CPC Class Codes: H05K 3/4617 : characterized by laminating only or mainly similar single-sided circuit boards
• CPC Class Codes: H05K 3/4641 : having integrally laminated metal sheets or special power cores
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 428/12361 : having aperture or cut
• CPC Class Codes: Y10T 428/12382 : Defined configuration of both thickness and nonthickness surface or angle therebetween [e.g., rounded corners, etc.]
• CPC Class Codes: Y10T 428/12556 : Organic component
• CPC Class Codes: Y10T 428/12569 : Synthetic resin
• CPC Class Codes: Y10T 428/12806 : Refractory [Group IVB, VB, or VIB] metal-base component
• CPC Class Codes: Y10T 428/12812 : Diverse refractory group metal-base components: alternative to or next to each other
• CPC Class Codes: Y10T 428/24777 : Edge feature
• CPC Class Codes: Y10T 428/31678 : Of metal
• CPC Class Codes: Y10T 428/31681 : Next to polyester, polyamide or polyimide [e.g., alkyd, glue, or nylon, etc.]

Abstract

This invention relates generally to a structure and process for thin film interconnect, and more particularly to a structure and process for a multilayer thin film interconnect structure with improved dimensional stability and electrical performance. The invention further relates to a process of fabrication of the multilayer thin film structures. The individual thin film structure is termed a compensator, and functions as both a ground/reference plane and as a stabilizing entity with regard to dimensional integrity. The compensator is comprised primarily of a metal sheet having a metallized via pattern and high-temperature stable polymer as an insulator.

Claims

1. A process for the fabrication of a compensator interconnect used in forming a multilayer thin-film structure, said process comprising the steps of,

a) forming at least one via hole in at least one metal foil,

b) securing said at least one metal foil having said at least one via hole to a partially cured first polymer layer that is formed on a rigid substrate,

c) covering the exposed surfaces of said metal foil with at least one second polymer, such that said second polymer covers the exposed surfaces of said metal foil and completely fills said at least one via hole,

d) subjecting the structure of step c) to a temperature of at least 300 degrees C., to cure said first and said second polymer,

e) forming at least one via hole through said at least one polymer filled via, such that said via hole extends through the entire thickness of said polymer,

f) filling said at least one via hole with at least one electrically conductive material to form a via metal stud, and

g) removing said rigid substrate to form said compensator interconnect.

2. The process of claim 1, wherein after step a) at least one layer of an adhesion metal is deposited on said metal foil, such that said adhesion metal covers the entire exposed metal foil surfaces and lines said at least one via hole.

3. The process of claim 1, wherein at least one or both of said polymer layers is a BPDA-PDA polyimide layer.

4. The process of claim 1, wherein in step a) said metal foil has a knife-edge configuration in said at least one via hole.

5. The process of claim 1, wherein said via stud is formed by electroplating, sputtering, or evaporation.

6. The process of claim 1, wherein the rough surfaces are planarized by polishing techniques.

7. The process of claim 2, wherein said adhesion metal is selected from a group consisting of chromium, copper, nickel, tantalum, titanium, or alloys thereof.

8. The process of claim 1, wherein the material for said at least one metal layer is selected from a group consisting of copper, Invar, molybdenum, tungsten, or alloys thereof.

9. The process of claim 1, wherein said electrically conductive material to form said via metal stud is selected from a group consisting of aluminum, copper, gold, tungsten or alloys thereof.

10. The process of claim 1, wherein at least one of said polymer is a high-temperature stable polyimide derived from polyamic acid or polyamic ester precursors.

11. The process of claim 1, wherein at least one of said polymer is low thermal expansion polyimide BPDA-PDA with in-plane thermal coefficient of expansion of 5-6 ppm/degrees C. at 100 degrees C. and formed from biphenic dianhydride--p-phenylene diamine.

12. The process of claim 1, wherein said at least one metal layer is made from an electrically conductive material.

13. The process of claim 1, wherein in step b) said rigid substrate has at least one electrically conductive etch-stop layer.

14. The process of claim 13, wherein at least one electrical circuit is formed, with said etch-stop layer.

15. The process of claim 14, wherein said etch-stop layer is integrated into said multilayer thin-film structure.

16. The process of claim 1, wherein in step f) said at least one via hole has a conformal coating of a metal seed layer.

17. The process of claim 16, wherein said metal seed layer is selected from a group consisting of chromium or copper or alloys thereof.

18. A process for the fabrication of a compensator interconnect used in forming a multilayer thin-film structure, said process comprising the steps of,

a) forming at least one via hole in at least one metal foil,

b) securing said at least one metal foil having said at least one via hole to a partially cured first polymer layer that is formed on a rigid substrate,

c) covering the exposed surfaces of said metal foil with at least one second polymer, such that said second polymer covers the exposed surfaces of said metal foil and completely fills said at least one via hole,

d) subjecting the structure of step c) to a temperature of at least 300 degrees C., to cure said first and said second polymer,

e) forming at least one via hole through said at least one polymer filled via, such that said via hole extends through the entire thickness of said polymer,

f) forming at least one blind via hole through said polymer such that said blind via hole exposes a portion of said metal foil,

g) filling said at least one via hole and said at least one blind via hole with at least one electrically conductive material to form a via metal stud and a blind via metal stud, and

h) removing said rigid substrate to form said compensator interconnect.

19. The process of claim 18, wherein after step a) at least one layer of an adhesion metal is deposited on said metal foil, such that said adhesion metal covers the entire exposed metal foil surfaces and lines said at least one via hole.

20. The process of claim 18, wherein at least one or both of said polymer layers is a BPDA-PDA polyimide layer.

21. The process of claim 18, wherein in step a) said metal foil has a knife-edge configuration in said at least one via hole.

22. The process of claim 18, wherein said via metal stud or said blind via metal stud is formed by electroplating, sputtering, or evaporation.

23. The process of claim 18, wherein the rough surfaces are planarized by polishing techniques.

24. The process of claim 19, wherein said adhesion metal is selected from a group consisting of chromium, copper, nickel, tantalum, titanium, or alloys thereof.

25. The process of claim 18, wherein the material for said at least one metal layer is selected from a group consisting of copper, Invar, molybdenum, tungsten, or alloys thereof.

26. The process of claim 18, wherein said electrically conductive material to form said via metal stud or said blind via metal stud is selected from a group consisting of aluminum, copper, gold, tungsten or alloys thereof.

27. The process of claim 18, wherein at least one of said polymer is a high-temperature stable polyimide derived from polyamic acid or polyamic ester precursors.

28. The process of claim 18, wherein at least one of said polymer is low thermal expansion polyimide BPDA-PDA with in-plane thermal coefficient of expansion of 5-6 ppm/degrees C. at 100 degrees C. and formed from biphenic dianhydride--p-phenylene diamine.

29. The process of claim 18, wherein said at least one metal layer is made from an electrically conductive material.

30. The process of claim 18, wherein in step b) said rigid substrate has at least one electrically conductive etch-stop layer.

31. The process of claim 30, wherein at least one electrical circuit is formed with said etch-stop layer.

32. The process of claim 31, wherein said etch-stop layer is integrated into said multilayer thin-film structure.

33. The process of claim 18, wherein in step g) said at least one via hole and said at least one blind via hole has a conformal coating of a metal seed layer.

34. The process of claim 33, wherein said metal seed layer is selected from a group consisting of chromium or copper or alloys thereof.