Uniport interface for a bar code reading instrument

• US 5,233,169 A
• Filed: 10/31/1991
• Issued: 08/03/1993
• Est. Priority Date: 10/31/1991
• Status: Expired due to Fees

• Current Assignee: Welch Allyn Incorporated
• Original Assignee: PTO (Safe Fleet Holdings LLC)
• Inventors: Longacre, Andrew Jr.
• Primary Examiner(s): Shepperd, John
• Assistant Examiner(s): SHAMI, KHALED
• Application Number:
  US07/785,849
• Time in Patent Office: 642 Days
• Field of Search: 235/462, 235/470, 235/472, 250/214 R, 250/557, 250/566
• US Class Current: 235/462.15
• CPC Class Codes: G06K 17/0022 arrangements or provisious for transferring data to distant stations, e.g. from a sensing device "transfer between computer elements G06F13/00 "; data-transmission H04L
• CPC Class Codes: G06K 7/10851 Circuits for pulse shaping, amplifying, eliminating noise signals, checking the function of the sensing device basic electronic circuitry H03

Abstract

An optical bar code reading instrument has a uniport interface circuit which accepts through a common terminal both charging current for the reader'"'"'s internal rechargeable battery and incoming digital electric information signals. The uniport interface also allows digital electrical signals produced by the instrument to pass through the same terminal.

Claims

1. In an optical bar code reader in which first digital electrical information signals are generated and which is responsive to second digital electrical information signals generated by a source external of said reader, said reader having an internal battery and an input-output terminal for connecting a source of voltage for charging said battery, the improvement comprising an interface circuit connected to said terminal, said interface circuit including output means for applying said first signals as output signals to said input-output terminal, means connected to said terminal for passing current of sufficient magnitude to charge said battery, and input means operative upon said second digital electrical information signals when said source is connected to said input-output terminal for applying said second digital electrical signals to said reader.

2. The improvement according to claim 1 wherein said charging current passing means comprises a unidirectionally conductive device connected between the input-output terminal and said battery to prevent discharge current from flowing from said battery to said input-output terminal.

3. The improvement according to claim 1 wherein said input means comprises a DC reference voltage source and a unidirectionally conductive device connected between said reference voltage source and said input-output terminal and defining a junction therebetween, said terminal being connected to said junction to provide a path for said second signals into said reader.

4. The improvement according to claim 1 wherein said output means comprises a logic device having means for inverting electrical signals, said logic device having an input and an output, and a transistor having means responsive to said first signals for the operation thereof in a pull down mode, said transistor being connected between said logic device and said input-output terminal with said first signals entering at the input of said logic device.

5. The improvement according to claim 1 wherein said input-output terminal comprises a jack having a receptacle for receiving a plug, said jack having dual contacts and a switch operated by said plug, one of said dual contacts being connected to ground, said switch being in an open state when said jack is in receipt of said plug and in a closed state when said jack is not in receipt of said plug, said reader having a memory, and means for applying said first signals to said memory when said switch is in a closed state.

6. The improvement according to claim 1 wherein said charging current passing means comprises a first unidirectionally conductive device connected between the input-output terminal and said battery to prevent discharge current from flowing from said battery to said input-output terminal, said input means comprises a DC reference voltage and a second unidirectionally conductive device connected between said reference voltage and said input-output terminal, with said second signals being applied to said reader from a point between said reference voltage and said second conductive device, said output means comprises a logic device having means for inverting electrical signals, said logic device having an input and an output, and a transistor with means responsive to said first signals for operation thereof in a pull-down mode, said transistor being connected between said logic device and said input-output terminal with said first signals being applied at the input of said logic device, and wherein said input-output terminal comprises a jack having a receptacle for receiving a plug, said jack having dual contacts and a switch operated by said plug, one of said dual contacts being connected to ground and the other of said contacts being connected to said first unidirectionally conductive device, said switch being in an open state when said jack is in receipt of said plug and in a closed state when said jack is not in receipt of said plug, said reader having a memory, and means for applying said first signals to said memory when said switch is in a closed state.

7. The improvement according to claim 2 wherein said unidirectionally conductive device is a diode having an anode and a cathode, an electrical resistance connected between said input-output terminal and said diode for passing charging current from said source through said diode, and wherein said battery has a positive and a negative terminal, said positive terminal being connected to the cathode of said diode and a voltage regulating means, and said negative terminal being connected to ground.

8. The improvement according to claim 3 wherein an electrical resistance is connected between said source and said unidirectionally conductive device, said device being a diode with an anode and a cathode, the anode of said diode being connected to said resistance and said cathode being connected to said terminal to connect said diode as a reverse biased diode switch, and wherein said input data appear at the cathode of said diode.

9. The improvement according to claim 4 wherein said output means further comprises an electrical resistance, said logic device is a logic inverter, said pull-down transistor is an NPN type transistor having an emitter, a base and a collector, said resistance is connected between said base and the output of said logic inverter, said collector is connected to said input-output terminal, and said emitter is connected to ground, and wherein said first signals are applied to the input of said logic inverter.

10. The improvement according to claim 6 wherein said first device is a first diode having an anode and a cathode, a first resistance is connected between said input-output terminal and said first diode, input electrical charging current from said source to said battery flowing through said first diode and said first resistance, said battery has a positive and a negative terminal, said positive terminal being connected to both the cathode of said first diode and said reader, and said negative terminal being connected to ground, a second electrical resistance is connected between said source and said second unidirectionally conductive device, said second unidirectionally conductive device being a second diode with an anode and a cathode, the cathode of said second diode being connected to both said first resistance and said first diode, the anode of said second diode being connected to said second resistance and said cathode of said second diode being connected to connect said second diode as a reverse biased diode switch, input data signals appear at the cathode of said second diode, said output means further comprises a third electrical resistance, said logic device is a logic inverter, said pull-down transistor is an NPN type transistor having an emitter, a base and a collector, said third resistance is connected between said base and the output of said logic inverter, said collector is connected to the cathode of said second diode, and said emitter is connected to ground, and wherein said first signals are received at the input of said logic inverter.

26. The improvement according to claim 10 wherein said charging voltage is supplied by a battery charging circuit, said charging circuit comprising a transformer with a primary and a secondary winding, a diode and a capacitor, said secondary winding being connected to one end of said diode, the other end of said diode being connected to said plug, and said capacitor connected between said secondary winding and the junction of said diode and said plug.

11. In a bar code reader system having a reader with an internal battery and a single terminal for connecting a source of voltage for charging said battery and for sending first electrical data signals as output signals from said reader and receiving second electrical data signals as input to said reader, said reader having a jack with dual contacts, the improvement comprising an adapter for use as an interface between said reader and an external input-output device, said adapter including output means for applying said first signals from said reader as output signals to said input-output device, input means for applying said second signals from said input-output device as input signals to said reader, and a dual contact plug receivable in said terminal, one contact being common, the other contact being connected to said input and output means.

12. The improvement according to claim 11 wherein said output means comprises a DC power supply, a current limiting resistance connected between said DC power supply and said plug, a transistor with means for operating said transistor in a pull down mode, said transistor having a base, a collector and an emitter connected between said plug, said input-output device and ground, and a voltage pull-down resistance connected between said collector and said power supply, said transistor acting to invert said first signals.

13. The improvement according to claim 11, wherein said input means comprises a transistor with means for operating said transistor in a pull-down mode, said transistor having an emitter, a collector and a base connected between each terminal of said plug and said input-output device.

14. The improvement according to claim 11 wherein said output means comprises a DC power supply, a first current limiting resistance connected between said DC power supply and said plug, a first transistor with means for operating said transistor in a pull down mode, said transistor having a first base, a first collector and a first emitter connected between said plug, said input-output device and ground, and a voltage pull-down resistance connected between said first collector and said power supply, said first transistor acting to invert said first signals, and wherein said input means comprises a second transistor with means for operating said transistor in a pull down mode, said transistor having a second emitter, a second collector and a second base connected between each terminal of said plug and said input-output device.

15. The improvement according to claim 12 wherein said output means also comprises a current limiting resistance between said base and said plug, said current limiting resistance acting as a current limiter for said base.

16. The improvement according to claim 13 wherein said input means also comprises a unidirectionally conductive device connected between said emitter and said base, said unidirectionally conductive device being a diode and acting as a voltage snubber to prevent damage to said transistor, and a current limiting resistance acting to limit the flow of current to said base.

17. The improvement according to claim 14 wherein said output means also comprises a first current limiting resistance between said first base and said plug, said first current limiting resistance acting as a current limiter for said first base, said input means also comprises a unidirectionally conductive device connected between said second emitter and said second base, said unidirectionally conductive device being a diode and acting as a voltage snubber to prevent damage to said second transistor, and a second current limiting resistance acting to limit the flow of current to said second base.

21. The improvement according to claim 16 wherein said output means comprises a dual stage transistor circuit, said transistor circuit comprising a first transistor and a second transistor, said first transistor being connected between said jack, said plug and said second transistor, said second transistor being connected between said jack, said first transistor and said input-output device.

24. The improvement according to claim 21 wherein said output means further comprises a snubbing diode connected across said inductor, said snubbing diode preventing excess current from flowing to the base of said first transistor, said first transistor is a PNP type transistor with a first collector, a first base and a first emitter, said second transistor is an NPN type transistor with a second collector, a second base and a second emitter, said first base being connected to each of said diode, said inductor and said plug, said first emitter being connected to each of said inductor, said diode and said jack, said first collector being connected to said second base, said second collector being connected to said first emitter, and said second emitter being connected to said input-output device, and wherein said output means also comprises a base current limiting resistance connected between said first collector and said second base.

18. In a bar code reader system having a reader with an internal battery and a single terminal for connecting a source of voltage for charging said battery and for sending first electrical data signals as output signals to an input-output device, said first signals being generated in said reader, and receiving second electrical data signals as input from said reader, said second signals being generated in said input-output device, said reader having a jack with dual contacts, the improvement comprising an adapter for use as an interface between said reader and both said voltage source and an external input-output device, said adapter including means for passing current of sufficient magnitude to charge said battery, output means for applying said first signals as output signals to said input-output device, input means in which said second signals are generated in said input-output device for applying said second signals to said reader, and a plug to be received in said terminal.

19. The improvement according to claim 18 wherein said current passing means comprises a power jack, said jack receiving battery charging current from said source, and an inductor connected between said jack and said plug.

20. The improvement according to claim 18 wherein said input means comprises a transistor with means for operating said transistor in a pull-down mode, said transistor having an emitter, a base and a collector connected between ground, said input-output device and both said inductor and said plug.

22. The improvement according to claim 18 wherein said input means comprises a transistor having means for operating said transistor in a pull-down mode, said transistor having an emitter, a base and a collector connected between ground, said input-output device and both said inductor and said plug, and wherein said output means comprises a dual stage transistor circuit, said transistor circuit comprising a first transistor and a second transistor, said first transistor being connected between said jack, said plug and said second transistor, said second transistor being connected between said jack, said first transistor and said input-output device.

23. The improvement according to claim 20 wherein said input means further comprises a current limiting resistance connected between said input-output device and the base of said transistor, and a voltage snubbing diode connected between the base and the emitter of said transistor, said diode preventing damage to said transistor.

25. The improvement according to claim 22 wherein said input means further comprises a first base current limiting resistance connected between said input-output device and the base terminal of said first transistor, and a voltage snubbing diode connected between the base and the emitter of said first transistor, said diode preventing damage to said first transistor, and wherein said output means further comprises a snubbing diode connected across said inductor, said snubbing diode preventing excess current from flowing to the base of said first transistor, said first transistor is a PNP type transistor with a first collector, a first base and a first emitter, said second transistor is an NPN type transistor with a second collector, a second base and a second emitter, said first base being connected to each of said diode, said inductor and said plug, said first emitter being connected to each of said inductor, said diode and said jack, said first collector being connected to said second base, said second collector being connected to said first emitter, and said second emitter being connected to said input-output device, and wherein said output means also comprises a second base current limiting resistance connected between said first collector and said second base.