Double digitlines for multiple programming of prom applications and other anti-fuse circuit element applications

• US 5,233,206 A
• Filed: 11/13/1991
• Issued: 08/03/1993
• Est. Priority Date: 11/13/1991
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lowrey, Tyler A., Durcan, D. Mark, Lee, Roger R.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Hardy, David B.
• Application Number:
  US07/791,808
• Time in Patent Office: 629 Days
• Field of Search: 257/50, 257/163, 257/298, 257/530, 257/306, 257/532, 365/163, 365/225.7, 437/47, 437/48, 437/52, 437/53, 437/59
• US Class Current: 257/50
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention provides a programmable structure for programmable integrated circuits, such as programmable read-only memory (PROM) which utilizes one-sided ozone spacers constructed on the digitlines as well as on the wordlines thereby providing two, one time programmable nodes at each digit/word/digit'"'"' intersection. An oxide/nitride/oxide layer (ONO) is used as an interface between underlying parallel rows of digit lines, having one-sided ozone spacers, and overlying parallel columns of word lines, also having one-sided ozone spacers, and further overlying parallel rows'"'"' of digitlines'"'"' in a programmable read only memory. With a lower level of digitlines passing under a middle level of wordlines and an upper level of digitlines'"'"' passing over the middle level of wordlines, a row/column/digit'"'"' matrix is formed thereby providing a programmable row/column/row'"'"' matrix in a memory array. Each crossing point of the digit/word lines and the word/digit'"'"' lines in the matrix will be permanently programmed to either a one or a zero by rupturing the thin ONO dielectric interface by applying the appropriate voltage potential between the associated digit/word/digit'"'"' line conductors.

Claims

1. A programmable structure having first and second one-time programmable nodes in an integrated circuit comprising:

a) a patterned first conductor having an overlying patterned first dielectric;

b) a second dielectric adjacent the patterned sides of said first conductor and said first dielectric, said second dielectric being a first thick dielectric spacer on a first patterned side of said first conductor and said first dielectric;

c) a third dielectric layer blanketing said first thick dielectric spacer, said first dielectric and a second patterned side of said first conductor and said first dielectric;

d) a patterned second conductor overlying said first conductor, said second conductor having an overlying patterned fourth dielectric residing in intersecting angular fashion to said first conductor with said third dielectric being a first programmable interface therebetween, thereby forming said first programmable node;

e) a fifth dielectric adjacent the patterned sides of said fifth conductor and said fourth dielectric, said second dielectric being a second thick dielectric spacer on a first patterned side of said second conductor and said fourth dielectric;

f) a sixth dielectric ;

layer blanketing said second thick dielectric spacer, said fourth dielectric and a second patterned side of said second conductor and said fifth dielectric; and

g) a patterned third conductor overlying said second patterned conductor, said third conductor residing in intersecting angular fashion to said second conductor with said sixth dielectric being a second interface therebetween, thereby forming said second programmable node.

2. The programmable structure of claim 1 wherein said first programmable node is programmed by rupturing said third dielectric by applying a voltage potential between said first and said second conductors thereby producing an intercoupling pn junction therebetween and said second programmable node is programmed by rupturing said sixth dielectric by applying a voltage potential between said second and said third conductors thereby producing an intercoupling pn junction therebetween.

3. The programmable structure of claim 1 wherein said integrated circuit comprises a memory device.

4. The integrated circuit of claim 3 wherein said memory device comprises a programmable read only memory.

5. The integrated circuit of claim 3 wherein said memory device comprises a programmable logic array.

6. The integrated circuit of claim 3 wherein said memory device comprises programmable array logic.

7. The integrated circuit of claim 1 wherein said programmable structure is formed on a substrate comprising silicon.

8. The integrated circuit of claim 1 wherein said first, second, fourth and fifth dielectric layers comprise oxide.

9. The integrated circuit of claim 1 wherein said third and sixth dielectric layers comprise oxide/nitride/oxide.

10. The programmable structure of claim 1 wherein said second and fifth dielectric spacers comprise ozone.

11. The integrated circuit of claim 1 wherein said first, second and third conductors comprise doped polysilicon.

12. The integrated circuit of claim 11 wherein said said first and third polysilicon conductor doping is to an n-type conductivity and said second polysilicon conductor doping is to a p-type conductivity.

13. The integrated circuit of claim 11 wherein said said first and third polysilicon conductor doping is to a p-type conductivity and said second polysilicon conductor doping is to an n-type conductivity.