Method of manufacturing a liquid crystal display panel including photoconductive electrostatic protection

• US 5,233,448 A
• Filed: 05/04/1992
• Issued: 08/03/1993
• Est. Priority Date: 05/04/1992
• Status: Expired due to Term

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Wu, Biing-Seng
• Primary Examiner(s): Zazworsky, John
• Assistant Examiner(s): TRICE, RONALD
• Application Number:
  US07/877,711
• Time in Patent Office: 456 Days
• Field of Search: 359/72, 359/88, 359/59, 359/87, 257/452, 257/457, 361/56, 361/58, 361/91, 361/111
• US Class Current: 349/40
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: Y10S 345/904 Display with fail/safe testing feature

Abstract

A method of manufacturing a liquid crystal display panel by forming a plurality of spaced scan lines, a plurality of spaced orthogonal data lines, and contact pads for each line on a substrate. Forming an electrostatic discharge line and light controlled discharge devices, each device being joined to the discharge line and a contact pad. Next illuminating the discharge devices and completing the fabrication of the array of optical display elements on the substrate associated with scan and data lines, blocking the light from discharge devices and electrically testing the array. Then again illuminating the discharge devices while assembling a second substrate over the first substrate and inserting the liquid crystal material therebetween.

Claims

1. A substrate for a liquid crystal display panel including a thin film transistor array comprising:

a flat transparent substrate;

a plurality of spaced, parallel scan lines, and a plurality of spaced orthogonally arranged parallel data lines on said substrate;

a plurality of contact pads adjacent to the periphery of said substrate that are electrically connected to said scan lines and said data lines;

an array of thin film transistor display elements on said substrate that is operationally associated with said scan lines and said data lines;

a first annular electrostatic discharge line on said substrate that is located adjacent the periphery of said substrate outwardly of said contact pads;

a second annular electrostatic discharge line on said substrate located inwardly of said first discharge line and electrically connected to each of said contact pads; and

a plurality of light controlled electrostatic discharge devices adjacent said pads, each of said electrostatic discharge devices having two terminals with one terminal joined to said first electrostatic discharge line, and with the other terminal joined to one of said pads.

2. The substrate of claim 1 wherein each of said light controlled electrostatic discharge devices include a stripe of silicon material, and a layer area of heavily doped silicon material on each end of said stripe, and conductive metal terminals joined to said areas.

3. The substrate of claim 2 wherein said silicon material of said stripe is polycrystalline silicon.

4. The substrate of claim 2 wherein said silicon material of said stripe is amorphous silicon.

5. The substrate of claim 2 wherein both said stripe and layer areas are polycrystalline silicon.

6. The substrate of claim 2 wherein both said stripe and layer areas are amorphous silicon.

7. The substrate of claim 1 wherein said discharge device includes a photoconductor which when illuminated with light allows electrical conduction and when maintained dark does not allow electrical conduction.

8. A substrate for a liquid crystal display panel including a thin film transistor array comprising:

a flat transparent substrate;

a plurality of spaced, parallel scan lines, and a plurality of spaced orthogonally arranged parallel data lines on said substrate;

a plurality of contact pads adjacent to the periphery of said substrate that are electrically connected to said scan lines and said data lines;

an array of thin film transistor display elements on said substrate that is operationally associated with said scan lines and said data lines;

an annular electrostatic discharge line on said substrate that is located adjacent the periphery of said substrate outwardly of said contact pads; and

a plurality of light controlled electrostatic discharge devices adjacent said pads, each of said electrostatic discharge devices having two terminals with one terminal joined to said electrostatic discharge line, and with the other terminal joined to one of said pads.

14. The substrate of claim 8 wherein said discharge device includes a photoconductor which when illuminated with light allows electrical conduction and when maintained dark does not allow electrical conduction.

9. The substrate of claim 9 wherein each of said light controlled electrostatic discharge devices include a stripe of silicon material, and a layer area of heavily doped silicon material on each end of said stripe, and conductive metal terminals joined to said areas.

10. The substrate of claim 9 wherein said silicon material of said stripe is polycrystalline silicon.

11. The substrate of claim 9 wherein said silicon material of said stripe is amorphous silicon.

12. The substrate of claim 9 wherein both said stripe and layer areas are polycrystalline silicon.

13. The substrate of claim 9 wherein both said stripe and layer areas are amorphous silicon.

15. A method of manufacturing a liquid crystal display panel comprising:

forming a thin film transistor array on a first glass substrate, said array including a plurality of spaced parallel scan lines, a plurality of orthogonally arranged spaced parallel data lines, a plurality of contact pads adjacent to the periphery of the substrate that are electrically connected to said scan and data lines, an array of thin film transistors and pixel electrodes that are operationally associated with said scan lines and said data lines;

forming at least one first electrostatic discharge line on said first substrate spaced outwardly from said pads;

forming a plurality of light controlled electrostatic discharge devices adjacent said plurality of pads, each of said discharge devices having two terminals with one terminal joined to said discharge line and the other terminal joined to one of said pads;

electrically first testing said array while temporarily blocking out light from said discharge devices thereby making the devices non-conductive and isolating said discharge line from said pads;

forming a common electrode on a second glass substrate;

assembling said first substrate and said second substrate in closely spaced alignment;

illuminating said discharge devices to electrically short the line and pads, and injecting liquid crystal material in the space between said first and second substrates;

electrically second testing said array while temporarily blocking out light from said discharge devices thereby making the devices non-conductive and isolating said discharge line from said pads;

joining the pads to a suitable driver circuitry while illuminating said discharge devices; and

permanently blocking light from said discharge devices to electrically isolate said discharge line and pads for operation of said panel.

16. The method of claim 15 wherein each of said light controlled electrostatic discharge devices include a stripe of silicon material, and a layer area of highly doped silicon material on each end of said stripe, and conductive metal terminals joined to said areas.

17. The method of claim 16 wherein both said stripe and layer areas are polycrystalline silicon.

18. The method of claim 16 wherein both said stripe and layer areas are amorphous silicon.

19. The method of claim 16 wherein said discharge device includes a photoconductor which when illuminated with light allows electrical conduction and when maintained dark does not allow electrical conduction.

20. The method of claim 15 wherein said discharge lines are formed simultaneously with said scan lines.

21. The method of claim 15 wherein said discharge lines are formed simultaneously with said pixel electrodes.

22. The method of claim 15 wherein said discharge line is formed simultaneously with said data lines.

23. The method of claim 16 and further comprising:

said at least one first discharge line includes a second discharge line that is formed on said first substrate that is spaced outwardly from the first discharge line, said second discharge line being connected to each of said pads; and

removing said second discharge line before said first electrically testing said array;

said second discharge line serving to short said pads during fabrication of said thin film transistor array and thereby to eliminate damage to the array by electrostatic energy that is generated by the process steps.

24. The method of claim 23 wherein said second discharge line is removed by cutting the first substrate.

25. The method of claim 23 wherein each of said light controlled electrostatic discharge devices include a stripe of silicon material, and a later area of highly doped silicon material on each end of said stripe, and conductive metal terminals joined to said areas.

26. The method of claim 24 wherein both said stripe and layer areas are polycrystalline silicon.

27. The method of claim 24 wherein both said stripe and layer areas are amorphous silicon.

28. The method of claim 24 wherein said discharge device includes a photoconductor which when illuminated with light allows electrical conduction and when maintained dark does not allow electrical conduction.

29. The method of claim 22 wherein said discharge lines are formed simultaneously with said scan lines.

30. The method of claim 22 wherein said discharge lines are formed simultaneously with said pixel electrodes.

31. The method of claim 22 wherein said discharge line is formed simultaneously with said data lines.

32. The method of claim 15 wherein said at least one discharge line includes first and second discharge lines and said electrostatic discharge devices in the first line are shorted through a conductor stripe to said electrostatic discharge devices in the second line.